Closed-caption decoder, Asynchronous 1: synchronous – Lucent Technologies MN10285K User Manual
Page 248
Closed-Caption Decoder
Closed-Caption Decoder Registers
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
247
Panasonic
HDISTW: Sync Separator Detection Control Register 2
x’007ED6’
HDISTWW
x’007EF6’)
HDISTW[8:0]: HSYNC count setting the interval for sync separation detection
In this register, set the interval during which sync separation occurs. The
valid range is x’000’ to x’1FF’ and the recommended setting is x’0100’.
For NTSC format, set the register to 525 (dec), indicating an HSYNC
count of 525 VSYNC cycles. The recommended setting is x’0100’.
VCNT: VSYNC Separator Control Register
x’007ED8’
(VCNTW
x’007EF8’)
VSEPSEL: VSYNC signal select
0: 0H to 127H VSYNC separation mask
1: No mask
VSEPLMT[2:0]: VSYNC separation detection threshold
HVCOND: Sync Separator Status Register
x’007EDA’
(HVCONDW
x’007EFA’)
Use this register to monitor the status of the sync separator.
STPN: Status of clamping control pulse signal during STOP
COMPSY: Composite sync signal status
VSEP: VSYNC signal status
HSEP: HSYNC signal status
HLOCK: Sync detection
0: Asynchronous
1: Synchronous
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
HDIST
W8
HDIST
W7
HDIST
W6
HDIST
W5
HDIST
W4
HDIST
W3
HDIST
W2
HDIST
W1
HDIST
W0
Reset:
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
VSEP
SEL
—
—
—
—
—
VSEP
LMT2
VSEP
LMT1
VSEP
LMT0
Reset:
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
R/W:
R
R
R
R
R
R
R
R/W
R
R
R
R
R
R/W
R/W
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
STPN
COMP
SY
VSEP
HSEP
HLOCK
Reset:
0
0
0
1
1
0
0
0
R/W:
R
R
R
R
R
R
R
R