Lucent Technologies MN10285K - Manual (Page 60)

Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual Panasonic Semiconductor Development Company
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Panasonic
TM2UDICL: Timer 2 Underflow Interrupt Control Register (Low) x’00FC70’
TM2UDICL register detects and requests timer 2 underflow interrupts. It is
an 8-bit access register. Use the MOVB instruction to access it.
TM2UDIR: Timer 2 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM2UDID: Timer 2 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM2UDICH: Timer 2 Underflow Interrupt Control Register (High) x’00FC71’
TM2UDICH sets the priority level for and enables timer 2 underflow inter-
rupts. It is an 8-bit access register. Use the MOVB instruction to access it.
TM2UDLV[2:0]: Timer 2 underflow interrupt priority level
Sets the priority from 0 to 6.
TM2UDIE: Timer 2 underflow interrupt enable flag
0: Disable
1: Enable
TM1UDICL: Timer 1 Underflow Interrupt Control Register (Low) x’00FC72’
TM1UDICL detects and requests timer 1 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM1UDIR: Timer 1 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM1UDID: Timer 1 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit: 7 6 5 4 3 2 1 0
— — —
TM2UD
IR
— — —
TM2UD
ID
Reset: 0 0 0 0 0 0 0 0
R/W: R R R R/W R R R R
Bit: 7 6 5 4 3 2 1 0
—
TM2UD
LV2
TM2UD
LV1
TM2UD
LV0
— — —
TM2UD
IE
Reset: 0 0 0 0 0 0 0 0
R/W: R R/W R/W R/W R R R R/W
Bit: 7 6 5 4 3 2 1 0
— — —
TM1UD
IR
— — —
TM1UD
ID
Reset: 0 0 0 0 0 0 0 0
R/W: R R R R/W R R R R