Closed-caption decoder, Tie this bit to 0 – Lucent Technologies MN10285K User Manual

Page 238

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Closed-Caption Decoder

Closed-Caption Decoder Registers

MN102H75K/F75K/85K/F85K LSI User Manual

Panasonic Semiconductor Development Company

237

Panasonic

For designs using the closed-cap-

tion decoder, always tie the FCCNT

register to x’0008’.

FCCNT: VBI Decoding Format Select Register

x’007E00’

(FCCNTW

x’007E20’)

This register contains the settings for selecting either a hardware or soft-

ware slice level and for setting the data capture format. When you do not
use a bit or field in this register, tie it to the setting indicated below.

FCPSEL: Hard/soft sampling start position select

0: Select hardware calculation
1: Select software setting (set in SFTSTAP[10:0] field of STAP)

SYNCSEL: Sync signal select (HSYNC/VSYNC)

Tie this bit to 0.

HCNTSEL[1:0]: HSYNC count value select

When this field is unused, tie it to b’00’.

00: When odd, add 1 to the HSYNC count value

01: When even, add 1 to the HSYNC count value
10: No change to the HSYNC count value

11: Reserved

SLICESEL: Hard/soft slice level select

0: Select hardware calculation
1: Select software setting

SLICELD[2:0]: Slice level load timing select

When this field is unused, tie it to b’000’.

000: 1H

100: 1 field

001: 2H

101: 2 fields

010: 4H

110: 4 fields

011: 8H

111: 8 fields

SLPULSEL: Polarity select for the CRI cycle transition detection

0: Detect 0 to 1 transitions
1: Detect 1 to 0 transitions

CRICSEL: Detection interval select for the CRI frequency width

0: CRI capture interval only

1: CRI capture interval and transition detection interval

NCRIGSEL: Sampling pulse generation interval

0: Disable the CRI capture interval
1: Enable the CRI capture interval

CNTSTAP[4:0]: Caption data sampling start position

The higher the setting in this field, the later the start position. The valid
range is x’00’ to x’1F’.

Bit:

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

FCP
SEL

SYNC

SEL

HCNT

SEL1

HCNT

SEL0

SLICE

SEL

SLICE

LD2

SLICE

LD1

SLICE

LD0

SLPU

L

SEL

CRIC

SEL

NCRI

G

SEL

CNT

STAP4

CNT

STAP3

CNT

STAP2

CNT

STAP1

CNT

STAP0

Reset:

0

0

0

0

0

0

0

0

0

0

0

0

1

0

0

0

R/W:

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

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