Interrupts, Disable 1: enable, No interrupt requested 1: interrupt requested – Lucent Technologies MN10285K User Manual
Page 57: Interrupt undetected 1: interrupt detected, Sets the priority from 0 to 6, Vbiie: vbi (1) interrupt enable flag
Interrupts
Interrupt Control Registers
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
56
Panasonic
VBIICH: VBI (1) Interrupt Control Register (High)
x’00FC67’
VBIICH enables VBI (1) interrupts. It is an 8-bit access register. Use the
MOVB instruction to access it.
The priority level for VBI (1) interrupts is written to the TM4CBLV[2:0]
field of the TM4CBICH register.
VBIIE: VBI (1) interrupt enable flag
0: Disable
1: Enable
TM5CBICL: Timer 5 Compare/Capture B Interrupt Control Register (Low) x’00FC68’
TM5CBICL detects and requests timer 5 compare/capture B interrupts. It
is an 8-bit access register. Use the MOVB instruction to access it.
TM5CBIR: Timer 5 compare/capture B interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM5CBID: Timer 5 compare/capture B interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM5CBICH: Timer 5 Compare/Capture B Interrupt Control Register (High)x’00FC69’
TM5CBICH sets the priority level for and enables timer 5 compare/capture
B interrupts. It is an 8-bit access register. Use the MOVB instruction to
access it.
TM5CBLV[2:0]: Timer 5 compare/capture B interrupt priority level
Sets the priority from 0 to 6.
TM5CBIE: Timer 5 compare/capture B interrupt enable flag
0: Disable
1: Enable
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
VBI
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM5CB
IR
—
—
—
TM5CB
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
TM5CB
LV2
TM5CB
LV1
TM5CB
LV0
—
—
—
TM5CB
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R/W
R/W
R/W
R
R
R
R/W