Interrupts, No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected – Lucent Technologies MN10285K User Manual
Page 68: Disable 1: enable, Vbivwir: vbivsync (2) interrupt request flag, Vbivwid: vbivsync (2) interrupt detect flag, Vbivwie: vbivsync (2) interrupt enable flag, Tm3udir: timer 3 underflow interrupt request flag, Tm3udid: timer 3 underflow interrupt detect flag
Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
67
Panasonic
VBIVWICL: VBIVSYNC (2) Interrupt Control Register (Low)
x’00FC8A’
VBIVWICL detects and requests VBIVSYNC (2) interrupts. It is an 8-bit
access register. Use the MOVB instruction to access it.
VBIVWIR: VBIVSYNC (2) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIVWID: VBIVSYNC (2) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
VBIVWICH: VBIVSYNC (2) Interrupt Control Register (High)
x’00FC8B’
VBIVWICH enables VBIVSYNC (2) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
The priority level for VBIVSYNC (2) interrupts is written to the
VBIVLV[2:0] field of the VBIVICH register.
VBIVWIE: VBIVSYNC (2) interrupt enable flag
0: Disable
1: Enable
TM3UDICL: Timer 3 Underflow Interrupt Control Register (Low)
x’00FC8C’
TM3UDICL detects and requests timer 3 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM3UDIR: Timer 3 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM3UDID: Timer 3 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit:
7
6
5
4
3
2
1
0
—
—
—
VBIVW
IR
—
—
—
VBIVW
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
VBIVW
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM3UD
IR
—
—
—
TM3UD
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R