Interrupts, No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected – Lucent Technologies MN10285K User Manual
Page 54: Disable 1: enable, Iq5ir: external interrupt 5 interrupt request flag, Iq5id: external interrupt 5 interrupt detect flag, Iq5ie: external interrupt 5 interrupt enable flag
Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
53
Panasonic
IQ5ICL: External Interrupt 5 Interrupt Control Register (Low)
x’00FC5A’
IQ5ICL requests and verifies interrupt requests for external interrupt 5. It
is an 8-bit access register. Use the MOVB instruction to access it.
IQ5IR: External interrupt 5 interrupt request flag
0: No interrupt requested
1: Interrupt requested
IQ5ID: External interrupt 5 interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
IQ5ICH: External Interrupt 5 Interrupt Control Register (High)
x’00FC5B’
IQ5ICH enables external interrupt 5. It is an 8-bit access register. Use the
MOVB instruction to access it.
The priority level for external interrupt 5 is written to the IQ4LV[2:0] field
of the IQ4ICH register.
IQ5IE: External interrupt 5 interrupt enable flag
0: Disable
1: Enable
TM4CBICL: Timer 4 Compare/Capture B Interrupt Control Register (Low) x’00FC60’
TM4CBICL detects and requests timer 4 compare/capture B interrupts. It
is an 8-bit access register. Use the MOVB instruction to access it.
TM4CBIR: Timer 4 compare/capture B interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM4CBID: Timer 4 compare/capture B interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit:
7
6
5
4
3
2
1
0
—
—
—
IQ5IR
—
—
—
IQ5ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
IQ5IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM4CB
IR
—
—
—
TM4CB
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R