Interrupts, No interrupt requested 1: interrupt requested, Interrupt undetected 1: interrupt detected – Lucent Technologies MN10285K User Manual
Page 56: Disable 1: enable, Tm4udir: timer 4 underflow interrupt request flag, Tm4udid: timer 4 underflow interrupt detect flag, Tm4udie: timer 4 underflow interrupt enable flag, Vbiir: vbi (1) interrupt request flag, Vbiid: vbi (1) interrupt detect flag
Interrupts
Interrupt Control Registers
MN102H75K/F75K/85K/F85K LSI User Manual
Panasonic Semiconductor Development Company
55
Panasonic
TM4UDICL: Timer 4 Underflow Interrupt Control Register (Low)
x’00FC64’
TM4UDICL detects and requests timer 4 underflow interrupts. It is an 8-
bit access register. Use the MOVB instruction to access it.
TM4UDIR: Timer 4 underflow interrupt request flag
0: No interrupt requested
1: Interrupt requested
TM4UDID: Timer 4 underflow interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
TM4UDICH: Timer 4 Underflow Interrupt Control Register (High)
x’00FC65’
TM4UDICH enables timer 4 underflow interrupts. It is an 8-bit access regis-
ter. Use the MOVB instruction to access it.
The priority level for timer 4 underflow interrupts is written to the
TM4CBLV[2:0] field of the TM4CBICH register.
TM4UDIE: Timer 4 underflow interrupt enable flag
0: Disable
1: Enable
VBIICL: VBI (1) Interrupt Control Register (Low)
x’00FC66’
VBIICL detects and requests VBI (1) interrupts. It is an 8-bit access register.
Use the MOVB instruction to access it.
VBIIR: VBI (1) interrupt request flag
0: No interrupt requested
1: Interrupt requested
VBIID: VBI (1) interrupt detect flag
0: Interrupt undetected
1: Interrupt detected
Bit:
7
6
5
4
3
2
1
0
—
—
—
TM4UD
IR
—
—
—
TM4UD
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R
Bit:
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TM4UD
IE
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R
R
R
R
R/W
Bit:
7
6
5
4
3
2
1
0
—
—
—
VBI
IR
—
—
—
VBI
ID
Reset:
0
0
0
0
0
0
0
0
R/W:
R
R
R
R/W
R
R
R
R