Timers – Lucent Technologies MN10285K User Manual
Page 85
Timers
8-Bit Timer Setup Examples
Panasonic Semiconductor Development Company
MN102H75K/F75K/85K/F85K LSI User Manual
84
Panasonic
4.5.2
Setting Up an Interval Timer Using Timers 1 and 2
In this example, timers 1 and 2 are cascaded to divide B
OSC
/4 by 60,000 and
generate an underflow interrupt.
1.
Disable timer 1 and 2 counting in the timer 1 and 2 mode registers
(TM1MD, TM2MD). This step is unnecessary immediately after a reset,
since TM1MD and TM2MD reset to 0.
TM1MD (example)
x’00FE21’
TM2MD (example)
x’00FE22’
2.
Cancel all existing interrupt requests and enable timer 2 underflow inter-
rupts. To do this, set the TM2UDLV[2:0] bits of TM2UDICH (priority level
4 in this example), set the TM2UDIE bit to 1, set the TM2UDIR bit of
TM2UDICL to 0, set the TM1UDIE bit of TM1UDICH to 0, and set the
TM1UDIR bit of TM1UDICL to 0. (Note that you set the priority level for
both timer 1 and 2 interrupts in the timer 2 interrupt control register.) From
this point on, an interrupt request is generated whenever timer 2 underflows.
Timer 1 underflows are unused.
Figure 4-11 Configuration Example of Interval Timer Using Timers 1 and 2
Figure 4-12 Block Diagram of Interval Timer Using Timers 1 and 2
Bit:
7
6
5
4
3
2
1
0
TM1
EN
TM1
LD
—
—
—
—
TM1
S1
TM1
S0
Setting:
0
0
0
0
0
0
0
0
Bit:
7
6
5
4
3
2
1
0
TM2
EN
TM2
LD
—
—
—
—
TM2
S1
TM2
S0
Setting:
0
0
0
0
0
0
0
0
B
OSC
(24 MHz)
Timer 2
underflow
interrupt
Timer 1
16-bit timer
(Divide by 60,000)
(x'EA60')
1/4
(Divide by 4)
Timer 2
P2
P6
P4
P5
CORE
Interrupts
Timers 0-3
Timers 4-5
ROM, RAM
Bus Controller
Serial I/Fs
ADC