Table 4-18. gfer0 bit definitions, Table 4-19. gfer1 bit definitions, Table 4-20. gfer2 register bitmap – Intel PXA26X User Manual
Page 123: Table 4-18, Table 4-20
Intel® PXA26x Processor Family Developer’s Manual
4-15
System Integration Unit
Table 4-18. GFER0 Bit Definitions
Physical Address
0x40E0_003C
GFER0
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FE31
FE30
FE29
FE28
FE27
FE26
FE25
FE24
FE23
FE22
FE21
FE20
FE19
FE18
FE17
FE16
FE15
FE14
FE13
FE12
FE1
1
FE10
FE9
FE8
FE7
FE6
FE5
FE4
FE3
FE2
FE1
FE0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
FE[x]
GPIO Pin ‘x’ Falling Edge Detect Enable (where x = 0 through 31):
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
Table 4-19. GFER1 Bit Definitions
Physical Address
0x40E0_0040
GFER1
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
FE
63
FE
62
FE
61
FE
60
FE
59
FE
58
FE
57
FE
56
FE
55
FE
54
FE
53
FE
52
FE
51
FE
50
FE
49
FE
48
FE
47
FE
46
FE
45
FE
44
FE
43
FE
42
FE
41
FE
40
FE
39
FE
38
FE
37
FE
36
FE
35
FE
34
FE
33
FE
32
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:0>
FE[x]
GPIO PIN ‘X’ FALLING EDGE DETECT ENABLE (where x = 32 through 63):
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin
Table 4-20. GFER2 Register Bitmap
Physical Address
0x40E0_0044
GPIO Falling Edge Detect Enable
Register2 (GFER2)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
FE89
FE88
FE87
FE86
FE85
FE84
FE83
FE82
FE81
FE80
FE79
FE78
FE77
FE76
FE75
FE74
FE73
FE72
FE71
FE70
FE69
FE68
FE67
FE66
FE65
FE64
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:26>
—
Reserved
<25:0>
FE[x]
GPIO PIN ‘X’ FALLING EDGE DETECT ENABLE (where x = 64 through 89):
0 – Disable falling-edge detect enable.
1 – Set corresponding GEDR status bit when a falling edge is detected on the GPIO pin