Table 17-2. rbr bit definitions, 2 transmit holding register (thr), Table 17-3. thr bit definitions – Intel PXA26X User Manual
Page 595: 3 divisor latch registers (dll and dlh), Section 17.5.3, Table 17-2
Intel® PXA26x Processor Family Developer’s Manual
17-11
Hardware UART
17.5.2
Transmit Holding Register (THR)
In non-FIFO mode, the Transmit Holding Register (THR) holds the data byte(s) to be transmitted
next. When the
Transmit Shift Register (TSR) is emptied, the contents of the THR are loaded in the
TSR and the LSR[TDRQ] is set to a 1
Section 17.5.11, “Line Status Register (LSR)” on
).
In FIFO mode, a write to the THR puts data into the end of the FIFO. The data at the front of the
FIFO is loaded to the TSR when that register is empty. The Transmit Holding Register bit
definitions are shown in
17.5.3
Divisor Latch Registers (DLL and DLH)
The HWUART contains a programmable baud rate generator that can take the 14.7456 MHz-fixed-
input clock and divide it by a number that is between 1 and 2
16
–1. The baud rate generator output
frequency is 16 times the baud rate. Two 8-bit latches store the divisor in a 16-bit binary format.
Table 17-2.
RBR Bit Definitions
Physical Address
0x4160 0000 (DLAB=0)
Read Buffer Reg. (RBR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
Byte 0
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
Bits
Access
Name
Description
31:8
N/A
—
Reserved – Read as unknown and must be written as zero.
7:0
R
Byte 0
BYTE 0
Table 17-3.
THR Bit Definitions
Physical Address
0x4160 0000 (DLAB=0)
Transmit Holding Reg. (THR)
PXA26x Processor Family Hardware
UART
User
Settings
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
Byte 0
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
0
0
0
0
0
Bits
Access
Name
Description
31:8
N/A
—
Reserved – Read as unknown and must be written as zero.
7:0
Write
Byte 0
BYTE 0