Intel PXA26X - Manual (Page 148)

4-40 Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
4.4.2.3 Operating System Timer Watchdog Match Enable Register (OWER)
The watchdog enable register contains a single control bit (bit 0) that enables the watchdog
function. This bit is set by writing a one to it and can only be cleared by one of the reset functions
such as, hardware reset, sleep reset, watchdog reset, and GPIO reset.
Table 4-46 shows the bitmap of the OS Watchdog Match Enable Register.
Table 4-45. OIER Bit Definitions
Physical Address
0x40A0_001C
OS Timer Interrupt Enable
Register (OIER)
System Integration Unit
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E3 E2 E1 E0
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0
Bits Name Description
<31:4> — Reserved
<3> E3
INTERRUPT ENABLE CHANNEL 3:
0 – A match between OSMR3 and the OS Timer will NOT assert OSSR[M3].
1 – A match between OSMR3 and the OS Timer asserts OSSR[M3].
<2> E2
INTERRUPT ENABLE CHANNEL 2:
0 – A match between OSMR2 and the OS Timer will NOT assert OSSR[M2].
1 – A match between OSMR2 and the OS Timer asserts OSSR[M2].
<1> E1
INTERRUPT ENABLE CHANNEL 1:
0 – A match between OSMR1 and the OS Timer will NOT assert OSSR[M1].
1 – A match between OSMR1 and the OS Timer asserts OSSR[M1].
<0> E0
INTERRUPT ENABLE CHANNEL 0:
0 – A match between OSMR0 and the OS Timer will NOT assert OSSR[M0].
1 – A match between OSMR0 and the OS Timer asserts OSSR[M0].
Table 4-46. OWER Bit Definitions
Physical Address
0x40A0_0018
OS Timer Watchdog Match Enable
Register (OWER)
System Integration Unit
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
WM
E
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bits Name Description
<31:1> — Reserved
<0> WME
WATCHDOG MATCH ENABLE:
0 – OSMR3 match will NOT cause a reset of the processor
1 – OSMR3 match causes a reset of the processor.