Intel PXA26X - Manual (Page 352)

9-14 Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Bus Interface Unit
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Figure 9-8. Master-Receiver Read from Slave-Transmitter
Figure 9-9. Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-
Transmitter Write to Slave-Receiver
Figure 9-10. A Complete Data Transfer
Master to Slave Slave to Master
START Slave Address
R/nW
1
ACK
Data
Byte
ACK
Data
Byte
STOP
N Bytes + ACK
ACK
Default
Slave-Receive
Mode
First Byte Read
START
Slave R/nW
1
ACK
Data
Byte
ACK
Data
Byte
N Bytes + ACK
Read
ACK Sr
Slave R/nW
0
ACK
Data
Byte
ACK
Data
Byte
STOP
N Bytes + ACK
Write
ACK Address Address
Master to Slave Slave to Master
Repeated
Start
Data Chaining
SDA
SCL
Start
Condition
Address R/nW ACK Data ACK Data
1-7 8 9 8 9 8 9 1-7 1-7
ACK Stop
Condition
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