Intel PXA26X - Manual (Page 449)

Intel® PXA26x Processor Family Developer’s Manual 12-39
Universal Serial Bus Device Controller
12.6.9.1 Interrupt Mask Endpoint x (IMx), where x is 8 through 15.
The UICR1[IMx] bit is used to mask or enable the corresponding endpoint interrupt request,
USIR1[IRx]. When the mask bit is set, the interrupt is masked and the corresponding bit in the
USIR1 register is not allowed to be set. When the mask bit is cleared and an interruptible condition
occurs in the endpoint, the appropriate interrupt bit is set. Programming the mask bit to a 1 does not
affect the current state of the interrupt bit. It only blocks future zero to one transitions of the
interrupt bit.
Table 12-20. UDC Interrupt Control Register 1
0h 4060 0054 UICR1 Read/Write
Bit 31:8 7 6 5 4 3 2 1 0
Reserved IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8
Rese
t
X 1 1 1 1 1 1 1 1
Bits Name Description
0 IM8
INTERRUPT MASK FOR ENDPOINT 8:
0 – Transmit interrupt enabled
1 – Transmit interrupt disabled
1 IM9
INTERRUPT MASK FOR ENDPOINT 9:
0 – Receive interrupt enabled
1 – Receive interrupt disabled
2 IM10
INTERRUPT MASK FOR ENDPOINT 10:
0 – Receive interrupt enabled
1 – Receive interrupt disabled
3 IM11
INTERRUPT MASK FOR ENDPOINT 11:
0 – Transmit interrupt enabled
1 – Transmit interrupt disabled
4 IM12
INTERRUPT MASK FOR ENDPOINT 12:
0 – Receive interrupt enabled
1 – Receive interrupt disabled
5 IM13
INTERRUPT MASK FOR ENDPOINT 13:
0 – Transmit interrupt enabled
1 – Transmit interrupt disabled.
6 IM14
INTERRUPT MASK FOR ENDPOINT 14:
0 – Receive interrupt enabled
1 – Receive interrupt disabled
7 IM15
INTERRUPT MASK FOR ENDPOINT 15:
0 – Transmit interrupt enabled
1 – Transmit interrupt disabled
31:8 — Reserved for future use