Intel PXA26X - Manual (Page 269)

Intel® PXA26x Processor Family Developer’s Manual 7-1
Liquid Crystal Display Controller
7
The liquid crystal display (LCD) controller provides an interface from the Intel® PXA26x
Processor Family to a passive (DSTN) or active (TFT) flat panel display. Monochrome and several
color pixel formats are supported (see
Section 7.1.1, “Features” on page 7-2 ).
This chapter covers these topics:
• Section 7.1, “Overview”
• Section 7.2, “Liquid Crystal Display Controller Operation”
• Section 7.3, “Detailed Module Descriptions”
• Section 7.4, “Liquid Crystal Display External Palette and Frame Buffers”
• Section 7.5, “Functional Timing”
• Section 7.6, “Liquid Crystal Display Register Descriptions”
7.1 Overview
The processor LCD controller supports single- or dual-panel displays. Encoded pixel data created
by the core is stored in external memory in a frame buffer in 1-, 2-, 4-, 8-, or 16-bit increments. The
data is fetched from external memory and loaded into a first-in first-out (FIFO) buffer on a demand
basis, using the LCD controller’s dedicated dual-channel DMA controller (DMAC). One channel is
used for single-panel displays and two are used for dual-panel displays.
Frame buffer data contains encoded pixel values that are used by the LCD controller as pointers to
index a 256-entry x 16-bit-wide palette. For 16-bit per pixel frame buffer entries, the palette RAM
is bypassed. Monochrome palette entries are 8-bits wide, and color palette entries are 16-bits wide.
The encoded pixel data determines the number of possible colors within the palette as:
• 1-bit-wide pixels address the top 2 locations of the palette
• 2-bit-wide pixels address the top 4 locations of the palette
• 4-bit-wide pixels address the top 16 locations of the palette
• 8-bit-wide pixels address any of the 256 entries within the palette
• 16-bit-wide pixels bypass the palette
When passive color 16-bit pixel mode is enabled, the color pixel values bypass the palette and are
fed directly to the LCD controller’s frame rate control logic. When active color 16-bit pixel mode
is enabled, the pixel value bypasses the palette and the frame rate control logic and is sent directly
to the LCD controller’s data pins. Optionally, the palette RAM is loaded for each frame by the LCD
controller’s DMAC.
Once the encoded pixel value is used to select a palette entry, the value programmed within the
entry is transferred to the frame rate control logic, which uses the temporal modulated energy
distribution (TMED) algorithm to produce the pixel data that is sent to the screen. Frame rate
control is a technique used to create additional color shades from palette entries by rapidly turning
on and off a pixel on the LCD screen. This is also known as temporal dithering. The data output