5 mmc_cmdat register, Table 15-10. mmc_cmdat register (sheet 1 of 2) – Intel PXA26X User Manual
Page 537
Intel® PXA26x Processor Family Developer’s Manual
15-25
MultiMediaCard Controller
15.5.5
MMC_CMDAT Register
The MMC_CMDAT register controls the command sequence. Writing to this register starts the
command sequence on the MMC bus when the MMC bus clock is turned on.
1
CRC_ON
CRC GENERATION ENABLE:
0 – Disables CRC generation and verification
1 – Enables CRC generation and verification
0
SPI_EN
SPI MODE ENABLE:
0 – Disables SPI mode
1 – Enables SPI mode
Table 15-9. MMC_SPI Register (Sheet 2 of 2)
Physical Address
4110_000c
MMC_SPI Register
MMC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
SPI_
C
S_
AD
DR
ESS
SPI_
C
S_
EN
CR
C_
O
N
SP
I_
EN
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
Table 15-10. MMC_CMDAT Register (Sheet 1 of 2)
Physical Address
4110_0010
MMC_CMDAT Register
MMC
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
MMC
_
D
MA
_
E
N
IN
IT
BU
SY
ST
REA
M
_
B
L
O
CK
WR
ITE
/R
E
A
D
DA
T
A
_
E
N
R
E
S
P
O
N
S
E
_
F
O
R
M
A
T[
1:
0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
Bits
Name
Description
31:8
—
Reserved
7
MMC_DMA_E
N
DMA MODE ENABLE:
0 – Program I/O mode
1 – DMA mode
When DMA mode is used, this bit is a mask on RXFIFO_RD_REQ and TXFIFO_WR_REQ
interrupts.
6
INIT
80 INITIALIZATION CLOCKS:
0 – Do not precede command sequence with 80 clocks
1 – Precede command sequence with 80 clocks