Intel PXA26X - Manual (Page 77)

Intel® PXA26x Processor Family Developer’s Manual 3-11
Clocks and Power Manager
During idle mode these resources are active:
• System unit modules (real-time clock, operating system timer, interrupt controller, general-
purpose I/O, and the clocks and power manager)
• Peripheral unit modules (DMA controller, LCD controller, and all other peripheral units)
• Memory controller resources
3.4.6.1 Entering Idle Mode
During idle mode, the clocks to the CPU core stop. All critical applications must be finished and
peripherals must be set up to generate interrupts when they require CPU attention. To enter the idle
mode, software selects idle mode in PWRMODE[M] (See
Section 3.7.2 ). An interrupt immediately
aborts idle mode and normal processing resumes. After software selects idle mode, the CPU waits
until all instructions in the pipeline are completed. When the instructions are completed, the CPU
clock stops and idle mode begins. In idle mode, interrupts are recognized as wake-up sources.
3.4.6.2 Behavior in Idle Mode
In idle mode the CPU clocks are stopped, but the remainder of the processor operates normally. For
example, the LCD controller can continue refreshing the screen with the same frame buffer data in
memory.
When ICCR[DIM] is cleared, any enabled interrupt wakes up the processor. When ICCR[DIM] is
set, only unmasked interrupts cause wake-up.
Enabled interrupts are those interrupts that are allowed at the unit level. The value in the Interrupt
Controller Mask Register prevents masked interrupts are from interrupting the core.
3.4.6.3 Exiting Idle Mode
Idle mode exits when any reset is asserted. Reset entry and exit sequences take precedence over
idle mode. When the reset exit sequence is completed, the CPU is not in idle mode. If the watchdog
timer is enabled, software must set the Watchdog Match Registers before it sets idle mode to ensure
that another interrupt brings the processor out of idle mode before the watchdog reset is asserted.
Use an RTC alarm or another OS timer channel for this purpose.
Any enabled interrupt causes idle mode to exit. When ICCR[DIM] is cleared, the Interrupt
Controller Mask Register (ICMR) is ignored during idle mode. This means that an interrupt does
not have to be unmasked to cause idle mode to exit. The idle mode exit sequence is:
1. A valid, enabled interrupt asserts
2. The CPU clocks restart
3. CPU resumes operation at the state indicated by CCLKCFG [TURBO]
Idle mode also exits when the nBATT_FAULT or nVDD_FAULT pin is asserted. When either pin
is asserted, idle mode exits in this sequence:
1. The nBATT_FAULT or nVDD_FAULT pin is asserted.
2. If the Imprecise Data Abort Enable (IDAE) bit in the Power Manager Control Register
(PMCR) is clear (not recommended), the processor enters sleep mode immediately.
3. If the IDAE bit is set, the nBATT_FAULT or nVDD_FAULT assertion is treated as a valid
interrupt to the clocks module and idle mode exits using its normal, interrupt-driven sequence.