Intel PXA26X - Manual (Page 617)

Intel® PXA26x Processor Family Developer’s Manual 18-1
Internal Flash
18
This chapter describes the flash interface for the Intel® PXA26x Processor Family. The PXA26x
processor family has three devices that contain internal Intel StrataFlash® memory:
• PXA261 processor – 128 megabit x 16 Intel StrataFlash® memory
• PXA262 processor – 256 megabit x 16 Intel StrataFlash® memory
• PXA263 processor – 256 megabit x 32 Intel StrataFlash® memory
For the best performance, configure one of the PXA26x processor family devices (in the list above)
in synchronous mode.
Note: This section describes the synchronous Intel StrataFlash® memory. All references to Intel
StrataFlash® memory is to the synchronous (K3) version.
18.1 Initialization
During boot-up, the Intel StrataFlash® memory exits reset in asynchronous mode. Configure the
PXA26x processor family BOOT_SEL pins as asynchronous flash memory for the correct bus
width. After boot-up, configure the memory controller in synchronous mode.
18.1.1 Intel StrataFlash® Memory Reset Configuration
Connect nRESET_OUT to nRST_F, for hardware reset, watchdog reset, and sleep mode to work
properly. GPIO reset does not work because the contents of the memory controller Synchronous
Static Memory Configuration Register (SXCNFG) are not reset, but the flash would be reset to
asynchronous mode. If GPIO reset operation is required, a state machine is necessary between
nRESET, nRESET_OUT, GPIO[1], and nRST_F to guarantee that nRST_F is asserted during
hardware reset, watchdog reset, and sleep mode, and not asserted during GPIO reset.
Figure 18-1
shows the required logic. GPIO_a is an unused GPIO that is driven low by software during the boot
sequence and left high during normal operation. After this is completed, then enable GPIO reset.
Figure 18-1. Flash Memory Reset Using State Machine
nS
nR
GPIO[1]
GPIO_a
Q
nRESET_OUT
nRESET
nRST_F
PXA26x