Intel PXA26X - Manual (Page 411)

Intel® PXA26x Processor Family Developer’s Manual 12-1
Universal Serial Bus Device
Controller
12
This section describes the Universal Serial Bus (USB) protocol and its implementation-specific
options for device controllers for the Intel® PXA26x Processor Family. These options include
endpoint number, type, and function; interrupts to the Intel® XScale™ Microarchitecture (core);
and a transmit/receive FIFO interface. A working knowledge of the USB standard is vital to using
this section effectively. The universal serial bus device controller (UDC) is USB-compliant and
supports all standard device requests issued by the host. UDC operation summaries and quick
reference tables are provided. Refer to the Universal Serial Bus Specification, revision 1.1, for a
full description of the USB protocol. The Universal Serial Bus Specification is available at
http://
www.usb.org .
The PXA26x processor family USB device controller has support for a 6-pin interface compatible
with the Phillips Semiconductors PDIUSBP11A transceiver with the MODE pin grounded and
SPEED pin driven high. Suspend is not supported with this interface, and if needed must be
implemented with a separate GPIO. Two of the pins are multiplexed with the FFUART, which
simplifies the physical interface for synchronization by allowing software to automatically choose
between a USB or UART interface.
To enable the 6 pin interface, the GPIO pins associated with it must be set to the appropriate
alternate function. When all the pins in the interface are enabled, the default USB interface pins,
USB_P and USB_N are automatically disabled. USB_P and USB_N must be driven to ground
when using the 6 pin interface. See
Section 4.1.2, “GPIO Alternate Functions” on page 4-3 for
details.
12.1 Universal Serial Bus Overview
The UDC supports 16 endpoints and can operate half-duplex at a rate of 12 Mbps (as a slave only,
not as a host or hub controller). The UDC supports four device configurations.
Configurations 1, 2,
and 3 each support two interfaces. Alternate interface settings are not supported. This allows the
host to accommodate dynamic changes in the physical bus topology. A configuration is a specific
combination of USB resources available on the device. An interface is a related set of endpoints
that present a device feature or function to the host.
The UDC transmits serial information that contains layers of communication protocols. Fields are
the most basic protocol. UDC fields include: sync, packet identifier (PID), address, endpoint, frame
number, data, and cyclic redundancy check (CRC). Fields are combined to produce packets. A
packet’s function determines the combination and number of fields that make up the packet. Packet
types include: token, start of frame, data, and handshake. Packets are assembled into groups to
produce transactions. Transactions fall into four groups: bulk, control, interrupt, and isochronous.
endpoint 0 is used only to communicate the control transactions that configure the UDC. Endpoint
0’s responsibilities include: connection, address assignment, endpoint configuration, bus
enumeration, and disconnection.
The UDC uses a dual-port memory to support FIFO operations. Each bulk and isochronous
endpoint FIFO structure is double buffered to enable the endpoint to process one packet as it
assembles another. The DMA and the core can fill and empty the FIFOs. An interrupt or DMA