Figure 4-2. interrupt controller block diagram, 2 interrupt controller register definitions, 1 interrupt controller mask register (icmr) – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
System Integration Unit
4.2.2
Interrupt Controller Register Definitions
The interrupt controller contains the following registers:
•
Interrupt Controller IRQ Pending register (ICIP)
•
Interrupt Controller FIQ Pending register (ICFP)
•
Interrupt Controller Pending register (ICPR)
•
Interrupt Controller Mask register (ICMR)
•
Interrupt Controller Level register (ICLR)
•
Interrupt Controller Control register (ICCR)
After a reset, the FIQ and IRQ interrupts are disabled within the CPU, and the states of all of the
interrupt controller registers are set to 0x0. The interrupt controller registers must be initialized by
software before interrupts are again enabled within the CPU.
4.2.2.1
Interrupt Controller Mask Register (ICMR)
The Interrupt Controller Mask register (ICMR) contains one mask bit per pending interrupt bit (25
total). The mask bits control whether a pending interrupt bit generates a processor interrupt (IRQ or
FIQ). When a pending interrupt becomes active, it is only processed by the CPU if the
corresponding ICMR mask bit is set to 1. While in IDLE mode, ICCR[DIM] must be set for the
mask to be effective, otherwise any interrupt source that makes a request sets the corresponding
pending bit and the interrupt is automatically processed, regardless of the state of its mask bit.
Mask bits allow periodic software polling of interruptible sources while preventing them from
actually causing an interrupt. The ICMR register is initialized to zero at reset, indicating that all
interrupts are masked and the ICMR has to be configured by the user to select the desired
interrupts.
Figure 4-2. Interrupt Controller Block Diagram
Interrupt Mask
Register (ICMR)
Interrupt Source
Bit
Interrupt Level
Register (ICLR)
FIQ
Interrupt
IRQ
Interrupt
to
Processor
to
Processor
Interrupt Pending
Register (ICPR)
FIQ Interrupt
Pending Register
IRQ Interrupt
Pending Register
24
24
All Other Qualified
Interrupt Bits
ICCR[DIM]=0 & IDLE mode=’1’
(ICFP)
(ICIP)