3 isochronous packet error endpoint 9 (ipe9), 4 isochronous packet error endpoint 14 (ipe14), 5 start of frame interrupt mask (sim) – Intel PXA26X User Manual

Page 454: 6 start of frame interrupt request (sir)

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12-44

Intel® PXA26x Processor Family Developer’s Manual

Universal Serial Bus Device Controller

12.6.12.3

Isochronous Packet Error Endpoint 9 (IPE9)

The isochronous packet error for Endpoint 9 is set if Endpoint 9 is loaded with a data packet that is
corrupted. This status bit is used in the interrupt generation of endpoint 9. To maintain
synchronization, software must monitor this bit when it services the SOF interrupt and reads the
frame number. This bit is not set if the token packet is corrupted or if the sync or PID fields of the
data packet are corrupted.

12.6.12.4

Isochronous Packet Error Endpoint 14 (IPE14)

The isochronous packet error for Endpoint 14 is set if Endpoint 14 is loaded with a data packet that
is corrupted. This status bit is used in the interrupt generation of endpoint 14. To maintain
synchronization, software must monitor this bit when it services the SOF interrupt and reads the
frame number. This bit is not set if the token packet is corrupted or if the sync or PID fields of the
data packet are corrupted.

12.6.12.5

Start of Frame Interrupt Mask (SIM)

The UFNHR[SIM] bit is used to mask or enable the SOF interrupt request. When
UFNHR[SIM]=1, the interrupt is masked and the SIR bit is not allowed to be set. When
UFNHR[SIM]=0, the interrupt is enabled and when an interruptible condition occurs in the
receiver, the UFNHR[SIR] bit is set. Setting UFNHR[SIM] to a 1 does not affect the current state
of UFNHR[SIR]. It only blocks future zero to one transitions of UFNHR[SIR].

12.6.12.6

Start of Frame Interrupt Request (SIR)

The interrupt request bit is set if the UFNHR[SIM] bit is cleared and an SOF packet is received.
The UFNHR[SIR] bit is cleared by writing a 1 to it.

Table 12-23. UDC Frame Number High Register (Sheet 1 of 2)

0h 4060 0060

UFNHR

Read

Bit

31:8

7

6

5

4

3

2

1

0

Reserved

SIR

SIM

IPE14

IPE9

IPE4

3-Bit Frame Number MSB

Rese

t

X

0

1

0

0

0

0

0

0

Bits

Name

Description

2:0

FNMSB

FRAME NUMBER MSB:

Most significant 3-bits of 11-bit frame number associated with last
receive SOF.

3

IPE4

ISOCHRONOUS PACKET ERROR ENDPOINT 4 (read/write 1 to clear):

1 – Status indicator that data in the endpoint FIFO is corrupted

4

IPE9

ISOCHRONOUS PACKET ERROR ENDPOINT 9 (read/write 1 to clear):

1 – Status indicator that data in the endpoint FIFO is corrupted

5

IPE14

ISOCHRONOUS PACKET ERROR ENDPOINT 14 (read/write 1 to
clear):

1 – Status indicator that data in the endpoint FIFO is corrupted

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