Intel PXA26X - Manual (Page 579)

Intel® PXA26x Processor Family Developer’s Manual 16-31
Network/Audio Synchronous Serial Protocol Serial Ports
Table 16-8. SSSR Bit Definitions (Sheet 1 of 3)
Physical Address
Base + 0x08
SSSR
PXA26x processor family Network/Audio
SSP Serial Ports
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
BC
E
CS
S
TU
R
R
e
ser
ved
TIN
T
R
e
ser
ved
RF
L
TFL RO
R
RF
S
TFS BS
Y
RN
E
TN
F
R
e
ser
ved
Reset ? ? ? ? ? ? ? ? 0 0 0 ? 0 ? ? ? 1 1 1 1 0 0 0 0 0 0 0 0 0 1 ? ?
Bits Access Name Description
31:24 — — Reserved
23 R/W BCE
BIT COUNT ERROR:
Indicates that the SSP has detected the SSPSFRM signal asserted at
an incorrect time. This bit will cause an interrupt if SSCR1[BCE] is set.
The SSP will ignore the current sample and the next sample in order to
re-synchronize with the master.
Write one to clear this bit.
0 – SSPSFRM has not been asserted out of synchronization.
1 – SSPSFRM has been asserted out of synchronization.
22 R CSS
CLOCK SYNCHRONIZATION STATUS:
A read-only bit that indicates the SSP is busy synchronizing the control
signals. This bit is only valid when the SSP is a slave to frame.
Software must wait until this bit is a 0 before allowing an external device
to assert the SSPSFRM signal.
0 – The SSP is ready for slave operations.
1 – The SSP is busy synchronizing slave mode signals.
21 R/W TUR
TRANSMIT FIFO UNDER RUN:
Indicates that the transmitter tried to send data from the transmit FIFO
when the transmit FIFO was empty. When set, an interrupt is generated
to the CPU that cannot be locally masked by any SSP port register bit.
Setting TUR does not generate any DMA service request. To clear
TUR, software sets it. TUR remains set until cleared by software writing
a one to it which also reset its Interrupt request. Writing a zero to this bit
does not affect TUR.
TUR can be set only when the port is a slave to the FRAME signal
(SSCR1[SFRMDIR] set) and is not set if the port is in receive-without-
transmit mode (SSCR1[RWOT] set).
Write one to clear this bit.
0 – Transmit FIFO has not experienced an under run
1 – Attempted read from the transmit FIFO when the FIFO was empty,
request interrupt.
20 — — Reserved
19 R/W TINT
RECEIVER TIME-OUT INTERRUPT:
Indicates that the receive FIFO has been idle (no samples received) for
the period of time defined by the value programmed within SSTO. This
interrupt can be masked by SSCR1[TINTE].
Write one to clear this bit.
0 – No Receiver Time-out pending
1 – Receiver Time-out pending
18:16 — — Reserved