Intel PXA26X - Manual (Page 618)

18-2 Intel® PXA26x Processor Family Developer’s Manual
Internal Flash
If watchdog reset is not necessary, a secondary GPIO can control nRESET_OUT using the
equation nRST_F = nRESET & (nRESET_OUT | GPIO_a). This allows sleep-mode entry to reset
the flash memory while keeping it in synchronous mode during a GPIO reset.
Figure 18-2 shows
the required logic. GPIO_a is an unused GPIO that is kept high during normal operation and driven
low before sleep-mode entry and held low during sleep mode.
18.1.2 BOOT_SEL[2:0] Configuration
The external BOOT_SEL[2:0] pins must be configured as 0b001 when using either the PXA261
processor or PXA262 processor.
The external BOOT_SEL[2:0] pins must be configured as 0b000 when using the PXA263
processor.
18.1.3 Determining the Size and Configuration of Flash Using
Software
If the same software is used for multiple versions of the PXA26x processor family, the software
must determine the size and organization of the Intel StrataFlash® memory present.
To determine the width of the Intel StrataFlash® memory, software can read MSC0[RBW0], which
is configured by the BOOT_SEL pins. If MSC0[RBW0] is configured as 32 bit, then it is a
PXA263 processor.
Otherwise, the software must determine if there is flash at the upper address boundary, after the
first 128-Mbit flash memory. To do this, the software checks for an alias copy of the vector table,
normally found at address 0x0, at address 0x0100 0000. If the vector table is not found, next check
to see if there is a second 128-Mbit flash memory present by writing 0x0090 to address
0x0100 0000, reading from address 0x0100 0000 and comparing the data returned with the
manufacturer’s code, 0x89. If no flash is detected at address 0x0100 0000, it is a PXA261
processor. If flash is detected, it is a PXA262 processor.
For additional information on device identifier codes, please see the Intel StrataFlash® memory
data sheet, order number 290737, available at http://developer.intel.com/design/flcomp/datashts/
290737.htm.
18.1.4 SXCNFG Configuration
Before setting SXCNFG, enable SDCLK[0] and set SDCLK[0] to run at one-half the memory-
clock frequency. Configure SXCNFG as shown in
Table 18-1 .
Figure 18-2. Flash Memory Reset Logic if Watchdog Reset is Not Necessary
GPIO_a
nRESET_OUT
nRESET
nRST_F
PXA26x