Intel PXA26X - Manual (Page 83)

Intel® PXA26x Processor Family Developer’s Manual 3-17
Clocks and Power Manager
— PM GPIO Sleep State registers (PGSR0, PGSR,1 and PGSR2)
— PM Wake-up Enable register (PWER)
— PM GPIO Falling-edge Detect Enable and PM GPIO Rising-edge Detect Enable registers
(PFER and PRER)
— OPDE bit in the Power Manager Configuration Register (PCFR)
— IDAE bit in PMCR
Note: Clear the PCFR[OPDE] bit to enable the 3.6864-MHz oscillator during sleep when fast-sleep wake
up is selected using the PMFWR[FWAKE] bit.
3.4.9.3 Entering Sleep Mode
Software uses the PWRMODE register to enter sleep mode (See Section 3.7.2 ).
If the external voltage regulator is failing or the main battery is low or missing, some systems must
enter sleep mode quickly. When nBATT_FAULT or nVDD_FAULT is asserted, the system is
required to shut down immediately.
To allow the assertion of nVDD_FAULT or nBATT_FAULT to cause an imprecise data abort, set
the Imprecise Data Abort Enable (IDAE) bit in the PMCR. Setting the IDAE bit in the PMCR
results in software executing the data abort handler routine as part of entering sleep mode. If the
IDAE bit is clear, the processor enters sleep mode immediately without executing the abort handler
routine.
Note: Use an exception handler to invoke sleep in response to a power fault event. Because software can
clear the PMFWR[FWAKE] bit and configure the power management IC to use PWR_EN to
disable the core power supply during sleep and thus minimize power consumption from a critically
low battery.
PSSR[VFS] and PSSR[BFS] can not be used prior to entering sleep mode to determine which type
of fault occurred, VDD fault or battery fault, respectively. If either nVDD_FAULT or
nBATT_FAULT signals are asserted or if both are asserted at the same time (and the IDAE bit of
the PMCR is set), the software data abort handler is called. Since there is only one common data
abort handler, software must first determine if one of the two nVDD_FAULT or nBATT_FAULT
assertion events resulted in an imprecise data abort by reading Coprocessor 7, Register 4, Bit 5
(PSFS). If the PSFS bit is cleared, neither a nVDD_FAULT or nBATT_FAULT assertion occurred
and the data abort handler was called for some other reason. If the PSFS bit is set, this indicates
either a nVDD_FAULT or nBATT_FAULT assertion occurred, but it is not possible to determine
which of the two faults was asserted. For either case, nVDD_FAULT or nBATT_FAULT assertion,
software should shut down the system as quickly as possible by performing the steps outlined
below to enter sleep mode.
Note: All addresses (data and instruction) used in the abort handler routines should be resident and
accessible in the memory page tables, that is system software developers should ensure no further
aborts occur while executing an abort handler. The processor does not support recursive (nested)
aborts. The system must not assert nBATT_FAULT or nVDD_FAULT signals more than once
before nRESET_OUT is asserted. System software can not return to normal execution following a
nBATT_FAULT or nVDD_FAULT. If a battery or VDD fault occurs while executing in the abort
mode, the abort handler is reentered. This condition of a recursive abort occurrence can be detected