Set mmc_i_mask to 0x1d, 11 stream read, Set mmc_i_mask to 0x1e – Intel PXA26X User Manual
Page 532: Wait for mmc_i_reg[data_tran_done] interrupt
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Intel® PXA26x Processor Family Developer’s Manual
MultiMediaCard Controller
8. Set MMC_I_MASK to 0x1d.
9. Wait for MMC_I_REG[PRG_DONE] interrupt. This interrupt indicates that the card has
finished programming. Software may wait for MMC_I_REG[PRG_DONE] interrupt or start
another command sequence on a different card.
10. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).
To address a different card, the software must send a select command to that card by sending a
basic no data command and response transaction. To address the same card, the software must wait
for MMC_I_REG[PRG_DONE] interrupt. This ensures that the card is not in the busy state.
15.4.11
Stream Read
In a stream read command, the software must stop the clock and set the registers as described in
section
Section 15.4.4, “No Data Command and Response Sequence”
. The following registers
must be set before the clock is turned on:
•
Set MMC_NOB register to ffffh.
•
Set MMC_BLKLEN register to the number of bytes per block.
•
Update the MMC_CMDAT register as follows:
— Write 0x01 to the MMC_CMDAT[RESPONSE_FORMAT].
— Set the MMC_CMDAT[DATA_EN] bit.
— Clear the MMC_CMDAT[WRITE/READ] bit.
— Set the MMC_CMDAT[STREAM_BLOCK] bit.
— Clear the MMC_CMDAT[BUSY] bit.
— Clear the MMC_CMDAT[INIT] bit.
•
Turn the clock on.
After it turns the clock on, the software must perform the following steps:
1. Wait for the response as described in section
Section 15.4.4, “No Data Command and
2. Read data from the MMC_RXFIFO FIFO and continue until all of the data has been read from
the FIFO.
3. Set the command registers for a stop transaction command (CMD12). If the DMA is being
used, the last descriptor must set the DMA to send an interrupt to signal that all the data has
been read.
4. Wait for a response to the stop transaction command as described in section
“No Data Command and Response Sequence”
5. Set MMC_I_MASK to 0x1e.
6. Wait for MMC_I_REG[DATA_TRAN_DONE] interrupt.
7. Read the MMC_STAT register to verify the status of the transaction (i.e. CRC error status).