1 subsequent interrupt status (sint), 2 branch status (bs), 3 end of frame status (eof) – Intel PXA26X User Manual
Page 312: Section 7.6.7.1, Section 7.6.7.2, Terrupt, Section 7.6.7.3
7-44
Intel® PXA26x Processor Family Developer’s Manual
Liquid Crystal Display Controller
7.6.7.1
Subsequent Interrupt Status (SINT)
SINT status is set when an unmasked interrupt occurs and there is already a pending interrupt. The
frame ID of the first interrupt is saved in the LCD controller interrupt ID register (LIIDR). SINT is
only set for bus error, start of frame, end of frame, and branch status interrupts.
Note:
If a branched-to descriptor has SOF set, both the SOF and branch interrupts are signalled at the
same time, and SINT is not set.
7.6.7.2
Branch Status (BS)
BS is set after the DMA controller has branched and loaded the descriptor from the frame branch
address in the frame branch register, and the branch interrupt (BINT) bit in the frame branch
register is set. When BS is set, an interrupt request is made to the interrupt controller (if the
interrupt controller is unmasked (LCCR0[BM]=0)).
In dual-panel mode (LCCR0[SDS=1]), both DMA channels are enabled, and BS is only set after
both channels’ frames have been fetched. BS remains set until cleared by software.
7.6.7.3
End Of Frame Status (EOF)
EOF status is set after the DMA controller has finished fetching a frame from memory and that
frame’s descriptor has the end-of-frame interrupt bit set (LDCMDx[EOFINT]=1). When EOF is
set, an interrupt request is made to the interrupt controller if it is unmasked (LCCR0[EFM]=0).
When dual-panel mode is enabled (LCCR0[SDS]=1), both DMA channels are enabled, and SOF is
set only after both channels’ frames have been fetched. EOF remains set until cleared by software.
2
BER
BUS ERROR STATUS – Nonmaskable interrupt (
0 – DMA has not attempted an access to reserved/nonexistent memory space.
1 – DMA has attempted an access to a reserved/nonexistent location in external memory.
1
SOF
START OF FRAME STATUS – Maskable interrupt (
):
0 – A new frame descriptor with its SOFINT bit set has not been fetched.
1 – The DMA has begun fetching a new frame with its SOFINT bit set.
0
LDD
LCD DISABLE DONE STATUS – Maskable interrupt (
0 – LCD has not been disabled or the last active frame completed.
1 – LCD has been disabled and the last active frame has completed.
Table 7-12. LCD Controller Status Register (Sheet 2 of 2)
Physical Address
0x4400_0038
LCD Controller Status Register 1
LCD Controller
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
reserved
SINT
BS
EO
F
QD
OU
IU
U
IU
L
AB
C
BE
R
SO
F
LD
D
Reset
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description