Intel PXA26X - Manual (Page 552)

16-4 Intel® PXA26x Processor Family Developer’s Manual
Network/Audio Synchronous Serial Protocol Serial Ports
16.4.2.2 Removing Trailing Bytes
In this case, no receive DMA service request is generated. To read out the trailing bytes, have the
software wait for the time-out interrupt and then read all remaining entries as indicated by
SSSR[RFL] and SSSR[RNE].
Note: The time-out interrupt must be enabled by setting SSCR1[TINTE].
16.4.3 Data Formats
Four pins transfer data between the PXA26x processor family and external CODECs or modems.
Although four serial-data formats exist, each has the same basic structure and in all cases the pins
are used as follows:
• SSPSCLK–Defines the bit rate at which serial data is driven onto and sampled from the port.
• SSPSFRM–Defines the boundaries of a basic data unit, comprised of multiple serial bits.
• SSPTXD–The serial data path for transmitted data, from system to peripheral.
• SSPRXD–The serial data path for received data, from peripheral to system.
A data frame can contain from four to 32-bits, depending on the selected protocol. Serial data is
transmitted most significant bit first. Four protocols are supported: TI Synchronous Serial
Protocol*, SPI, Microwire*, and a PSP.
The SSPSFRM function and use varies between each protocol.
• For the TI Synchronous Serial Protocol*, SSPSFRM is pulsed high for one (serial) data period
at the start of each frame. Master and slave modes are supported. TI Synchronous Serial
Protocol* is a full-duplex protocol.
• For the SPI* protocol, SSPSFRM functions as a chip select to enable the external device
(target of the transfer) and is held active-low during the data transfer (during continuous
transfers, the SSPSFRM signal can be either held low or pulsed depending upon the value of
SSCR1_x[SPH]). Master and slave modes are supported. SPI* is a full-duplex protocol.
• For the Microwire* protocol, SSPSFRM functions as a chip select to enable the external
device (target of the transfer) and is held active-low during the data transfer. Slave mode is not
supported for Microwire*. SSPSFRM for Microwire* is also held low during continuous
transfers. Microwire* is a half-duplex protocol.
• For the PSP, SSPSFRM is programmable in direction, delay, polarity, and width. Master and
slave modes are supported. PSP can be programmed to be either full or half duplex.
The SSPSCLK function and use varies between each protocol.
• For TI Synchronous Serial Protocol*, data sources switch transmit data on the rising edge of
SSPSCLK and sample receive data on the falling edge. Master and slave modes are supported.
• For SPI*, the SSP port lets programmers select which edge of SSPSCLK to use for switching
transmit data and for sampling receive data. In addition, users can move the phase of
SSPSCLK, shifting its active state one-half cycle earlier or later at the start and end of a frame.
Master and slave modes are supported.
• For Microwire*, both data sources switch (change to the next bit) transmit data on the falling
edge of SSPSCLK and sample receive data on the rising edge. Slave mode is not supported for
Microwire*.