Intel PXA26X - Manual (Page 80)

3-14 Intel® PXA26x Processor Family Developer’s Manual
Clocks and Power Manager
2. Disable the LCD controller or configure it to avoid the effects of an interruption in the LCD
clocks and data from the processor.
3. Configure peripheral units to handle a lack of DMA service for up to 500
µ
s. If a peripheral
unit can not function for 500
µ
s without DMA service, disable it.
4. Disable peripheral units that can not accommodate a 500
µ
s interrupt latency. The interrupts
generated during the frequency change sequence are serviced when the sequence exits.
5. Program the CCCR ( Section 3.6.1, “Core Clock Configuration Register (CCCR)” ) to reflect
the desired frequency.
3.4.8.2 Starting the Frequency Change Sequence
To start the frequency change sequence, software must set the Frequency Change Sequence bit
(FCS) in the CCLKCFG (See
Section 3.7.1 ). When software sets FCS, it may also set or clear other
bits in CCLKCFG. If software sets the TURBO bit in the same write, the CPU enters turbo mode
when the frequency change sequence exits.
After software sets the FCS:
1. The CPU clock stops and CPU interrupts are gated.
2. The memory controller completes all outstanding transactions in its buffers and from the CPU.
New transactions from the LCD or DMA controllers are ignored.
3. The memory controller places the SDRAM in self-refresh mode.
Note: Program the memory controller to ensure the correct self-refresh time for SDRAM, given the
slower of the current and desired clock frequencies.
3.4.8.3 Behavior During the Frequency Change Sequence
In the frequency change sequence, the processor’s PLL clock generator is in the process of locking
to the correct frequency and cannot be used. This means that interrupts cannot be processed.
Interrupts that occur during the frequency change sequence are serviced after the processor’s PLL
has locked. The 95.85 MHz and 147.46 MHz PLL clock generators are active and peripherals
(except memory controller, LCD controller, and DMA) may continue to operate normally, provided
they can accommodate the inability to process DMA or interrupt requests. DMA or interrupt
requests are not recognized until the frequency change sequence is complete.
The imprecise data abort is also not recognized and if nVDD_FAULT or nBATT_FAULT is
asserted, the assertion is ignored until the frequency change sequence exits. This means that the
processor does not enter sleep mode until the frequency change sequence is complete.
3.4.8.4 Completing the Frequency Change Sequence
The frequency change sequence exits when any reset is asserted. In hardware and watchdog resets,
the reset entry and exit sequences take precedence over the frequency change sequence and the
PLL resumes in its reset condition. In GPIO reset, the reset exit sequence is delayed while the PLL
relocks and the frequency is set to the desired frequency of the frequency change sequence.
If the watchdog timer is enabled during the frequency change sequence, set the Watchdog Match
Register to ensure that the frequency change sequence completes before the watchdog reset is
asserted.