6 ssp status register (sssr) – Intel PXA26X User Manual
Page 578
16-30
Intel® PXA26x Processor Family Developer’s Manual
Network/Audio Synchronous Serial Protocol Serial Ports
16.5.6
SSP Status Register (SSSR)
contains bit fields that signal overrun errors and the transmit and
receive FIFO service requests. Each of these hardware-detected events signals an interrupt request
to the interrupt controller. The status register also contains flags that indicate:
•
When the SSP port is actively transmitting data
•
When the transmit FIFO is not full
•
When the receive FIFO is not empty
One interrupt signal is sent to the interrupt controller for each SSP port. These events can cause an
interrupt:
•
Receiver time-out,
•
Receive FIFO overrun,
•
Receive FIFO request
•
Transmit FIFO request.
Bits that cause an interrupt signal the request as long as the bit is set. The interrupt clears when the
bits clear. Read and write bits are called status bits (status bits are referred to as sticky and once set
by hardware, they must be cleared by software); Read-only bits are called flags. Writing a 1 to a
status bit clears it; writing a 0 has no effect. Read-only flags are set and cleared by hardware; writes
have no effect. The reset state of read-write bits is zero and all bits return to their reset state when
SSCR0[SSE] is cleared. Additionally, some bits that cause interrupts have corresponding mask bits
in the control registers and are indicated in the section headings that follow.
Set the desired values for this register before enabling the SSP port (via SSCR0[SSE]).
These are read/write registers. Ignore reads from reserved bits. Write zeros to reserved bits.
6
R/W
TRFS
TEST RECEIVE FIFO SERVICE REQUEST:
0 – No receive FIFO service request is generated.
1 – Generates a non-maskable Interrupt to the CPU and a DMA
request for the receive FIFO.
5
R/W
TTFS
TEST TRANSMIT FIFO SERVICE REQUEST:
0 – No transmit FIFO service request is generated.
1 – Generates a non-maskable Interrupt to the CPU and a DMA
request for the transmit FIFO.
4:0
—
—
Reserved
Table 16-7.
SSITR Bit Definitions (Sheet 2 of 2)
Physical Address
Base + 0x0C
SSITR
PXA26x processor family Network/Audio
SSP Serial Ports
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
TR
O
R
TR
FS
TTF
S
Reserved
Reset
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
?
0
0
0
?
?
?
?
?
Bits
Access
Name
Description