Intel PXA26X - Manual (Page 603)

Intel® PXA26x Processor Family Developer’s Manual 17-19
Hardware UART
All reserved bits are read as unknown and must be written with a 0. The register organization and
the individual bit definitions are shown in
Table 17-11 on page 17-19 .
17.5.8 Auto-Baud Control Register (ABR)
The ABR controls the functionality and options for auto-baud-rate detection within the UART.
Through this register, users can enable/disable the auto-baud lock interrupt, direct either the
processor or UART to program the final baud rate in the Divisor Latch registers, and choose
between two methods used to calculate the final baud rate (see
Table 17-12 on page 17-20 ).
The auto-baud circuitry counts the number of clocks in the start bit and writes this count into the
Auto-Baud Count Register (ACR). It then interrupts the processor if ABR[ABLIE] is set. It also
automatically programs the Divisor Latch registers (DLL and DLH) if ABR[ABUP] bit is set.
Table 17-11. FOR Bit Definitions
Physical Address
0x4160_0024
FIFO Occupancy Reg. (FOR)
PXA26x processor family Hardware
UART
User
Settings
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Byte Count
Reset ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 0 0 0 0 0 0 0
Bits Access Name Description
31:7 N/A — Reserved – Read as unknown and must be written as zero.
6:0 R/W Byte Count Number of bytes (0-64) remaining in the receiver FIFO