Intel PXA26X - Manual (Page 348)

9-10 Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Bus Interface Unit
9.4.4.2 SDA Arbitration
Arbitration on the SDA line can continue for a long time because it starts with the address and R/
nW bits and continues through the data bits.
Figure 9-7 shows the arbitration procedure for two
masters. More than two masters may be involved if more than two masters are connected to the
bus. If the address bit and the R/nW are the same, the arbitration scheme considers the data.
Because the I
2
C bus has a wired-AND nature, a transfer does not lose data if multiple masters
signal the same bus states. If the address and the R/nW bit or the data they contain are different, the
master that sent the first low data bit loses arbitration and shuts off its data drivers. If the I
2
C unit
loses arbitration, it shuts off the SDA or SCL drivers for the rest of the byte transfer, sets the
ISR[ALD] bit, and returns to slave-receive mode.
Figure 9-6. Clock Synchronization During the Arbitration Procedure
CLK2
SCL
Wait
State
Start Counting
High Period
CLK1
The first master to complete its high
period pulls the SCL line low.
The master with the longest clock
period holds the SCL line low.
Figure 9-7. Arbitration Procedure of Two Masters
SDA
SCL
Data 1
Data 2
Transmitter 1 Leaves Arbitration
Data 1 SDA