Intel PXA26X - Manual (Page 330)

8-12 Intel® PXA26x Processor Family Developer’s Manual
Synchronous Serial Port Controller
8.7.2.1 Receive FIFO Interrupt Enable (RIE)
Use the Receive FIFO Interrupt Enable (RIE) bit to mask or enable the receive FIFO service
request interrupt. When RIE=0, the interrupt is masked and the interrupt controller ignores the state
of the receive FIFO Service Request (RFS) bit in the SSPC Status Register. When RIE=1, the
interrupt is enabled and, if RFS=1, an interrupt request is made to the interrupt controller. If RIE=0
neither the RFS bit’s current state nor the receive FIFO logic’s ability to set and clear the RFS bit is
affected. However, the interrupt request generation is blocked.
The RIE bit’s state does not affect the receive FIFO DMA request generation that is asserted when
RFS=1.
8.7.2.2 Transmit FIFO Interrupt Enable (TIE)
Use the Transmit FIFO Interrupt Enable (TIE) bit to mask or enable the transmit FIFO service
request interrupt. When TIE=0, the interrupt is masked and the interrupt controller ignores the state
of the Transmit FIFO Service Request (TFS) bit in the SSPC Status Register. When TIE=1, the
interrupt is enabled and, if TFS=1, an interrupt request is made to the interrupt controller. If TIE=0,
neither the TFS bit’s current state nor the transmit FIFO logic’s ability to set and clear the TFS bit
is affected. However, the interrupt request generation is blocked.
The TIE bit’s state does not affect the transmit FIFO DMA request generation that is asserted when
TFS=1.
8.7.2.3 Loop Back Mode (LBM)
Use the loop back mode (LBM) bit to enable and disable the SSP transmit and receive logic. When
LBM=0, the SSP operates normally. The transmit and receive data paths are independent and
communicate via their respective pins. When LBM=1, the transmit serial shifter’s output is directly
connected internally to the receive serial shifter’s input.
9:6 TFT
TRANSMIT FIFO THRESHOLD:
Sets threshold level at which transmit FIFO generates an interrupt or DMA request. This
level must be set to the desired threshold value minus 1.
13:10 RFT
RECEIVE FIFO THRESHOLD:
Sets threshold level at which receive FIFO generates an interrupt or DMA request. This
level must be set to the desired threshold value minus 1.
31:14 — Reserved
Table 8-3. SSP Control Register 1 (SSCR1) Bitmap and Definitions (Sheet 2 of 2)
0x4100 0004 SSP Control Register 1 (SSCR1)
Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
RF
T
TF
T
MW
D
S
SP
H
SPO LB
M
TIE RI
E
Reset X 0x0 0x0 0 0 0 0 0 0
Bits Name Description