1 pwm control registers (pwm_ctrln), Table 4-50. pwm_ctrln bit definitions, 2 pwm duty cycle registers (pwm_dutyn) – Intel PXA26X User Manual
Page 153: Section 4.5.2.1, “pwm, 1 pwm control registers (pwm_ctrl n ), 2 pwm duty cycle registers (pwm_duty n )
Intel® PXA26x Processor Family Developer’s Manual
4-45
System Integration Unit
4.5.2.1
PWM Control Registers (PWM_CTRLn)
The PWMn Control Register, PWM_CTRLn, contains two fields:
•
PRESCALE – The PRESCALE field contains the 6-bit prescale counter load value. This field
allows the 3.6864-MHz-input clock PSCLK_PWMn, to be divided by values between 1
(PWM_CTL[PRESCALE] = 0) and 64 (PWM_CTL[PRESCALE] = 63).
Note:
The value of the divisor is one greater than the value programmed into the PRESCALE field.
•
PWM_SD – PWMn can shut down in one of two ways, gracefully or abruptly, depending on
the setting of PWM_CTRLn[PWM_SD]. If gracefully is chosen, then the duty cycle counter
completes its count before PWMn is shut down. If abruptly is chosen, then the prescale
counter and the duty cycle counter are reset to the reload values in their associated registers
and PWMn is immediately shut down.
Note:
During abrupt shut down the PWM_OUTn signal may be delayed by up to one PSCLK_PWMn
clock period.
shows the bitmap of the PWM Control registers.
4.5.2.2
PWM Duty Cycle Registers (PWM_DUTYn)
The PWM Duty Cycle register, PWM_DUTYn, contains two fields:
•
FDCYCLE
•
DCYCLE
Table 4-50. PWM_CTRLn Bit Definitions
Physical Address
0x40B0_0000
0x40C0_0000
PWM Control Registers
(PWM_CTRL0, PWM_CTRL1)
System Integration Unit
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reserved
PW
M
_
S
D
PRESCALE
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bits
Name
Description
<31:7>
—
Reserved
<6>
PWM_SD
PWMn SHUTDOWN METHOD:
0 – Graceful shutdown of PWMn when the clock enable bit in the CKEN register is
cleared.
1 – Abrupt shutdown of PWMn when the clock enable bit in the CKEN register is cleared.
<5:0>
PRESCALE
PWMn PRESCALE DIVISOR:
Determines the frequency of the PWM module clock (in terms of the 3.86-MHz clock)
PSCLK_PWMn = 3.6864 MHz / (PWM_CTRL[PRESCALE] + 1)