Intel PXA26X - Manual (Page 506)

14-10 Intel® PXA26x Processor Family Developer’s Manual
Inter-Integrated Circuit Sound Controller
14.6.1.2 Suggested TFTH and RFTH for DMA servicing
The DMA controller can only be programmed to send 8, 16, or 32 bytes of data. This corresponds
to 2, 4, or 8 FIFO samples.
Table 14-5 shows the recommended TFTH and RFTH values to prevent
transmit FIFO over-run errors and receive FIFO under-run errors.
14.6.2 Serial Audio Controller I
2
S /MSB-Justified Control Register
(SACR1)
This register specifically controls the I2S and MSB-Justified modes. Table 14-6 shows the bit
layout of SACR1.
Table 14-4. FIFO Write/Read table
EFWR STRF Description
0 x
Normal CPU/DMA write/read condition:
• A write access to the Data Register writes a transmit FIFO entry.
• A read access to the Data Register reads out a receive FIFO entry.
• I2SLINK reads from the transmit FIFO and writes to the receive
FIFO.
1 0
CPU or DMA only writes and reads transmit FIFO:
• A write access to the Data Register writes a transmit FIFO entry.
• A read access to the Data Register reads out a transmit FIFO entry.
• I2SLINK cannot read the transmit FIFO but can write to the receive
FIFO.
1 1
CPU or DMA only writes and reads receive FIFO:
• A write access to the Data Register writes a receive FIFO entry.
• A read access to the Data Register reads out a receive FIFO entry.
• I2SLINK can read the transmit FIFO but cannot write to the receive
FIFO.
Table 14-5. TFTH and RFTH Values for DMA Servicing
DMA Transfer Size # of FIFO entries TFTH Value RFTH Value
Min Max Min Max
8 Bytes 2 0 14 1 15
16 Bytes 4 0 12 3 15
32 Bytes 8 0 8 7 15