Intel PXA26X - Manual (Page 85)

Intel® PXA26x Processor Family Developer’s Manual 3-19
Clocks and Power Manager
Refer to Table 2-6, “Pin & Signal Descriptions for the PXA26x Processor Family” on page 2-9 for
the PXA26x processor family pin states during sleep mode reset and other resets.
3.4.9.5 Exiting Sleep Mode
Sleep mode exits when hardware reset is asserted. Hardware reset entry and exit sequences take
precedence over sleep mode.
Note: If hardware reset is asserted during sleep mode, the DRAM contents are lost because all states,
including memory controller configuration and information about the previous sleep mode, are
reset.
Normally, sleep mode exits in the sequence below. Any time the nBATT_FAULT pin is asserted,
the processor returns to sleep mode.
1. A pre-programmed wake up event from an enabled GPIO or RTC source occurs. If the
nBATT_FAULT pin is asserted, the wake up source is ignored.
2. The PWR_EN signal is asserted and the power manager waits for the external power supply to
stabilize if PMFWR[FWAKE] is cleared. After this, if nVDD_FAULT is asserted the
processor returns to sleep mode.
3. If PCFR[OPDE] and OSCC[OON] were set when sleep mode started, the 3.6864 MHz
oscillator is enabled and stabilizes. Otherwise, the 3.6864 MHz oscillator is already stable and
this step is bypassed.
4. The processor’s PLL clock generator is reprogrammed with the values in the CCCR and
stabilizes.
5. The sleep mode configuration in PWRMODE[M] is cleared.
6. The processor’s internal reset is deasserted and the CPU begins a normal boot sequence. When
the normal boot sequence begins, all of the processor’s units (except the RTC and portions of
the clocks and power manager and the memory controller) return to their predefined reset
settings.
7. The nRESET_OUT pin is deasserted. This indicates that the processor is about to perform a
fetch from the reset vector.
8. Clear PSSR[PH] before accessing GPIOs, this includes chip selects that are muxed with
GPIOs.
9. Clear PCFR[FS] and PCFR[FP] if either was set before sleep mode was triggered.
10. The SDRAM must transition out of self-refresh mode and into its idle state. See Chapter 6,
“Memory Controller” for details on configuring the SDRAM interface.
11. Software must examine the RCSR, to determine what caused the reboot, and the Power
Manager Sleep Status Register (PSSR), to determine what triggered sleep mode.
12. If the PSPR was used to preserve any critical states during sleep mode, software can now
recover the information.
If the nVDD_FAULT or nBATT_FAULT pin is asserted during the sleep mode exit sequence, the
system re-enters sleep mode in this sequence:
1. Regardless of the state of the IDAE bit:
— All GPIO edge detects and the RTC alarm interrupt are cleared.