2 trailing bytes, 3 operational flow for accessing codec registers, 7 clocks and sampling frequencies – Intel PXA26X User Manual
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Intel® PXA26x Processor Family Developer’s Manual
AC97 Controller Unit
does not set the codec-ready bit, GCR[PCRDY] for the primary codec or GCR[SCRDY] for the
secondary codec.
13.6.2
Trailing bytes
If the transmit buffers do not have 32-byte resolution, the trailing bytes in the transmit FIFO are not
transmitted. A transmit buffer must be padded with zeroes if it is smaller than a multiple of 32
bytes. Regardless of burst size, the DMA descriptor length must be a multiple of 32 bytes to
prevent audio artifacts from being introduced on the interface.
After the codec transmits the valid data, the ACUNIT records zeroes until nACRESET is
reasserted. If the codec transmitted data has a total buffer size smaller than a multiple of 32 bytes,
zeroes are recorded. A receive DMA request is made when the receive FIFO is half-full.
13.6.3
Operational Flow for Accessing Codec Registers
Software accesses the codec registers by translating a 7-bit codec address to a 32-bit processor
physical address. For details regarding the address translation, refer to
Software must read the Codec Access Register (CAR) to lock the AC-link. The AC-link is free if
the CAR[CAIP] bit is a 0. For details about the CAR, refer to
The read access to the CAR sets the CAR[CAIP] bit. The ACUNIT clears the CAR[CAIP] bit
when the codec-write or codec-read operation completes. Software can also clear the CAR[CAIP]
bit by writing a 0.
After it locks the AC-link, software can write or read a codec register using the appropriate
processor physical address.
The ACUNIT sets the GSR[CDONE] bit after the completion of a codec write operation. For
details, refer to
Table 13-9, “Global Status Register”
. Software clears this bit by writing a 1 to it.
To read a codec, the software must complete these steps:
1. Software issues a dummy read to the codec register. The ACUNIT responds to this read
operation with invalid data. The ACUNIT then initiates the read access across the AC-link.
2. When the codec read operation completes, the ACUNIT sets GSR[SDONE] to a 1. For details,
Table 13-9, “Global Status Register”
. Software clears this bit by writing a 1 it.
3. Software repeats the read operation as detailed in Step 1. The ACUNIT now returns the data
sent by the codec. The second read operation also initiates a read access across the AC-link.
4. The ACUNIT times-out the read operation if the codec fails to respond in four SYNC frames.
In this case, the second read operation returns a timed-out data value of 0x0000_FFFF.
13.7
Clocks and Sampling Frequencies
By default, the ACUNIT transmits and receives data at a sampling frequency of 48 KHz. It can,
however, sample data at frequencies less than 48 KHz if the codec supports on-demand slot
requests. The codec in this case executes a certain algorithm and informs the controller not to