Altera Transceiver PHY IP Core User Manual
Page 119
Signal Name
Direction
Description
xgmii_tx_dc[71:0]
Input
XGMII data and control for 8 lanes. Each lane
consists of 8 bits of data and 1 bit of control.
xgmii_tx_clk
Input
Clock for single data rate (SDR) XGMII TX
interface to the MAC. It should connect to
xgmii_
rx_clk
. The frequency is 156.25 MHz irrespective
of 1588 being enabled or disabled. Driven from the
MAC.
xgmii_rx_dc[71:0]
Output
RX XGMII data and control for 8 lanes. Each lane
consists of 8 bits of data and 1 bit of control.
xgmii_rx_clk
Input
Clock for SDR XGMII RX interface to the MAC.
The frequency is 156.25 MHz irrespective of 1588
being enabled or disabled.
1G/10GbE GMII Data Interface
gmii_tx_d[7:0]
Input
TX data for 1G mode. Synchronized to
tx_clkout_
1g
clock. The TX PCS 8B/10B module encodes this
data which is sent to link partner.
gmii_rx_d[7:0]
Output
RX data for 1G mode. Synchronized to
tx_clkout_
1g
clock. The RX PCS 8B/10B decoders decodes this
data and sends it to the MAC.
gmii_tx_en
Input
When asserted, indicates the start of a new frame. It
should remain asserted until the last byte of data on
the frame is present on gmii_tx_d.
gmii_tx_err
Input
When asserted, indicates an error. May be asserted
at any time during a frame transfer to indicate an
error in that frame.
gmii_rx_err
Output
When asserted, indicates an error. May be asserted
at any time during a frame transfer to indicate an
error in that frame.
gmii_rx_dv
Output
When asserted, indicates the start of a new frame. It
remains asserted until the last byte of data on the
frame is present on gmii_rx_d.
led_char_err
Output
10-bit character error. Asserted for one rx_clkout_
1g cycle when an erroneous 10-bit character is
detected.
led_link
Output
When asserted, indicates successful link synchroni‐
zation.
5-10
1G/10GbE PHY Data Interfaces
UG-01080
2015.01.19
Altera Corporation
1G/10 Gbps Ethernet PHY IP Core