Simulate the ip core, Simulate the ip core -4 – Altera Transceiver PHY IP Core User Manual
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Note: The Finish button may be unavailable until all parameterization errors listed in the messages
window are corrected.
8. Click Yes if you are prompted to add the Quartus II IP File (.qip) to the current Quartus II project.
You can also turn on Automatically add Quartus II IP Files to all projects.
You can now integrate your custom IP core instance in your design, simulate, and compile. While
integrating your IP core instance into your design, you must make appropriate pin assignments. You can
create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating
and not ready to map the design to hardware.
For some IP cores, the generation process also creates complete example designs. An example design for
hardware testing is located in the < variation_name > _example_design/example_project/ directory. An
example design for RTL simulation is located in the < variation_name > _example_design/simulation/
directory.
Note: For information about the Quartus II software, including virtual pins, refer to Quartus II Help.
Related Information
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Simulate the IP Core
This section describes how to simulate your IP core.
You can simulate your IP core variation with the functional simulation model and the testbench or
example design generated with your IP core. The functional simulation model and testbench files are
generated in a project subdirectory. This directory may also include scripts to compile and run the
testbench.
For a complete list of models or libraries required to simulate your IP core, refer to the scripts provided
with the testbench.
For more information about simulating Altera IP cores, refer to Simulating Altera Designs in volume 3 of
the Quartus II Handbook.
Related Information
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Simulate the IP Core
UG-01080
2015.01.19
Altera Corporation
Getting Started Overview