Altera Transceiver PHY IP Core User Manual
Page 26
To make the most effective use of this soft PCS and PMA configuration for Stratix IV GT devices, you can
group up to four channels in a single quad and control their functionality using one Avalon-MM PHY
management bridge, transceiver reconfiguration module, and low controller. As this figure illustrates, the
Avalon-MM bridge Avalon-MM master port connects to the Avalon-MM slave port of the transceiver
reconfiguration and low latency controller modules so that you can update analog settings using the
standard Avalon-MM interface.
Note: This configuration does not require that all four channels in a quad run the 10GBASE-R protocol.
Figure 3-2: Complete 10GBASE-R PHY Design in Stratix IV GT Device
To MAC
To Embedded
Controller
Avalon-MM
connections
10GBASE-R PHY - Stratix IV Device
SDR XGMII
72 bits @ 156.25 Mbps
To MAC
SDR XGMII
72 bits @ 156.25 Mbps
Avalon-MM
PHY
Management
Bridge
M
S
S
Low Latency
Controller
S
Transceiver
Reconfig
Controller
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
Alt_PMA
10GBASE-R
10.3 Gbps
10.3125 Gbps serial
To HSSI Pins
PCS
10GBASE-R
(64b/66b)
S
S
The following figures illustrate the 10GBASE-R in Arria V GT, Arria V GZ, and Stratix V GX devices.
3-2
10GBASE-R PHY IP Core
UG-01080
2015.01.19
Altera Corporation
10GBASE-R PHY IP Core