Altera Transceiver PHY IP Core - Manual (Page 669)

Chapter Document
Version
Changes Made
Deterministic
Latency PHY IP Core
2.6
Made the following changes:
• Corrected the description of
tx_datak
signal in Table 11-8:
Avalon-ST TX Interface.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
Stratix V Transceiver
Native PHY IP Core
2.6
Made the following changes:
• Removed the description for
rx_clklow
and
rx_fref
ports from
Table 12-38: Native PHY Common Interfaces.
• Removed the ports
rx_clklow
and
rx_fref
from Figure 12-5:
Stratix V Native PHY Common Interfaces.
• Updated the description of
rx_10g_clk33out
clock signal in
Table 12-44: Name Dir Synchronous to tx_10g_coreclkin/rx_10g_
coreclkin Description.
• Updated the description of
tx_pma_qpipullup
,
tx_pma_
qpipulldn
, and
rx_pma_qpipulldn
signals in Table 12:38 -
Native PHY Common Interfaces.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
• Added
ext_pll_clk
signal to Figure 12-5: Stratix V Native PHY
Common Interfaces and added its description in Table 12-38:
Native PHY Common Interfaces.
Arria V Transceiver
Native PHY IP Core
2.6
Made the following changes:
• Removed the description for
rx_clklow
and
rx_fref
ports from
Table 13-31: Native PHY Common Interfaces.
• Removed the ports
rx_clklow
and
rx_fref
from Figure 13-3:
Native PHY Common Interface Ports.
• Updated the descriptions of
tx_cal_busy
and
rx_cal_busy
interface signals.
• Added
ext_pll_clk
signal to Figure 13-3: Common Interface
ports and added its description in Table 13-18: Native PHY
Common Interfaces.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core 21-9
Additional Information for the Transceiver PHY IP Core Altera Corporation
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