Altera Transceiver PHY IP Core User Manual
Page 452
Table 14-32: Interlaken Disparity Generator and Checker Parameters
Parameter
Range
Description
Enable Interlaken TX disparity generator
On/Off
When you turn this option On, the 10G
PCS includes the disparity generator.
This option is available for the
Interlaken protocol.
Enable Interlaken RX disparity generator
On/Off
When you turn this option On, the 10G
PCS includes the disparity checker. This
option is available for the Interlaken
protocol.
Block Synchronization
The block synchronizer determines the block boundary of a 66-bit word for the 10GBASE-R protocol or a
67-bit word for the Interlaken protocol. The incoming data stream is slipped one bit at a time until a valid
synchronization header (bits 65 and 66) is detected in the received data stream. After the predefined
number of synchronization headers is detected, the block synchronizer asserts
rx_10g_blk_lock
to other
receiver PCS blocks down the receiver datapath and to the FPGA fabric. The block synchronizer is
designed in accordance with both the Interlaken protocol specification and the 10GBASE-R protocol
specification as described in IEEE 802.3-2008 Clause-49.
Table 14-33: Bit Reversal and Polarity Inversion Parameters
Parameter
Range
Description
Enable RX block synchronizer
On/Off
When you turn this option On, the 10G
PCS includes the RX block synchron‐
izer. This option is available for the
Interlaken and 10GBASE-R protocols.
Enable rx_10g_blk_lock port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10G_blk_lock
output port. This signal is asserted to
indicate the receiver has achieved block
synchronization. This option is available
for the Interlaken, 10GBASE-R, and
other protocols that user the PCS lock
state machine to achieve and monitor
block synchronization.
Enable rx_10g_blk_sh_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10G_blk_sh_err
output port. This signal is asserted to
indicate that an invalid sync header has
been received. This signal is active after
block lock is achieved. This option is
available for the Interlaken,
10GBASE-R, and other protocols that
user the PCS lock state machine to
achieve and monitor block synchroniza‐
tion.
UG-01080
2015.01.19
10G PCS Parameters for Arria V GZ Native PHY
14-41
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation