Altera Transceiver PHY IP Core User Manual
Page 313
Phase Compensation FIFO
The phase compensation FIFO assures clean data transfer to and from the FPGA fabric by compensating
for the clock phase difference between the low-speed parallel clock and FPGA fabric interface clock. The
following table describes the options for the phase compensation FIFO.
Table 12-12: Phase Compensation FIFO Parameters
Parameter
Range
Description
TX FIFO mode
low_latency
register_fifo
The following 2 modes are possible:
• low_latency : This mode adds 3-4 cycles of
latency to the TX datapath.
• register_fifo : In this mode the FIFO is
replaced by registers to reduce the latency
through the PCS. Use this mode for
protocols that require deterministic
latency, such as CPRI.
RX FIFO mode
low_latency
register_fifo
The following 2 modes are possible:
• low_latency : This mode adds 2-3 cycles of
latency to the TX datapath.
• register_fifo : In this mode the FIFO is
replaced by registers to reduce the latency
through the PCS. Use this mode for
protocols that require deterministic
latency, such as CPRI.
Enable tx_std_pcfifo_full port
On/Off
When you turn this option On, the TX Phase
compensation FIFO outputs a FIFO full status
flag.
Enable tx_std_pcfifo_empty port
On/Off
When you turn this option On, the TX Phase
compensation FIFO outputs a FIFO empty
status flag.
Enable rx_std_pcfifo_full port
On/Off
When you turn this option On, the RX Phase
compensation FIFO outputs a FIFO full status
flag.
Enable rx_std_pcfifo_empty port
On/ Off
When you turn this option On, the RX Phase
compensation FIFO outputs a FIFO empty
status flag.
Byte Ordering Block Parameters
The RX byte ordering block realigns the data coming from the byte deserializer. This block is necessary
when the PCS to FPGA fabric interface width is greater than the PCS datapath. Because the timing of the
RX PCS reset logic is indeterminate, the byte ordering at the output of the byte deserializer may or may
not match the original byte ordering of the transmitted data. The following table describes the byte
ordering block parameters.
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY
12-15
Stratix V Transceiver Native PHY IP Core
Altera Corporation