Altera Transceiver PHY IP Core - Manual (Page 210)

“Section 4.2.3 Link Equalization Procedure for 8.0 GT/s Data Rate” in the PCI Express Base Specification,
Rev. 3.0 provides detailed information about the four-stage link equalization procedure. A new LTSSM
state, Recovery.Equalization with Phases 0–3, reflects progress through Gen3 equalization. Phases 2 and 3
of link equalization are optional; however, the link must progress through all four phases, even if no
adjustments occur. Skipping Phases 2 and 3 speeds up link training at the expense of link BER optimiza‐
tion.
Related Information
PHY Interface for the PCI Express Architecture PCI Express 3.0
Phase 0
Phase 0 includes the following steps:
1. Upstream component enters Phase 0 of equalization during Recovery.Rcvrconfig by sending EQ TS2
training sets with starting presets for the downstream component. EQ TS2 training sets may be sent at
2.5 GT/s or 5 GT/s.
2. The downstream component enters Phase 0 of equalization after exiting Recovery.Speed at 8 GT/s. It
receives the starting presets from the training sequences and applies them to its transmitter. At this
time, upstream component has entered Phase 1 and is operating at 8 GT/s.
3. To move to Phase 1, the receiver must have a BER < 10 -4 and should be able to decode enough
consecutive training sequences.
4. The downstream component must detect training sets with Equalization Control (EC) bits set to 2’b01
in order to move to EQ Phase 1.
Phase 1
During Phase 1 of equalization process, the link partners exchange FS (Full Swing) and LF (Low
Frequency) information. These values represent the upper and lower bounds for the TX coefficients. The
receiver uses this information to calculate and request the next set of transmitter coefficients.
1. Once training sets with EC bits set to 1’b0 are captured on all lanes, the upstream component moves to
EQ Phase 2 sending EC=2’b10 along with starting pre-cursor, main cursor, and post-cursor
coefficients.
2. The downstream component detects these new training sets, and moves to EQ Phase 2.
Phase 2 (Optional)
This section describes the (optional) Phase 2.
During Phase 2, the Endpoint tunes the TX coefficients of the Root Port. The TS1 Use Preset bit
determines whether the Endpoint uses presets for coarse resolution or coefficients for fine resolution.
Note: If you are using the PHY IP Core for PCI Express (PIPE) PCI Express as an Endpoint, you cannot
perform Phase 2 tuning. The PIPE interface does not provide any measurement metric to the Root
Port to guide coefficient preset decision making. The Root Port should reflect the existing
coefficients and move to the next phase. The default Full Swing (FS) value advertized by Altera
device is 40 and Low Frequency (LF) is 13.
If you are using the PHY IP Core for PCI Express (PIPE) PCI Express as Root Port, the End Point can
tune the Root Port TX coefficients.
8-22 Phase 0
UG-01080
2015.01.19
Altera Corporation PHY IP Core for PCI Express (PIPE)
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