Altera Transceiver PHY IP Core User Manual
Page 321
Parameter
Range
Description
Enable rx_std_wa_patternalign port
On/Off
Enables the optional
rx_std_wa_patterna-
lign
control input port. A rising edge on this
signal causes the word aligner to align the
next incoming word alignment pattern when
the word aligner is configured in manual
mode.
Enable rx_std_wa_a1a2size port
On/Off
Enables the optional
rx_std_wa_a1a2size
control input port.
Enable rx_std_wa_bitslipboundarysel
port
On/Off
Enables the optional
rx_std_wa_bitslip-
boundarysel
status output port.
Enable rx_std_wa_bitslip port
On/Off
Enables the optional
rx_std_wa_bitslip
control input port.
Enable rx_std_wa_runlength_err port
On/Off
Enables the optional
rx_std_wa_runlength_
err
control input port.
Bit Reversal and Polarity Inversion
These functions allow you to reverse bit order, byte order, and polarity to correct errors and to accommo‐
date different layouts of data. The following table describes these parameters.
Parameter
Range
Description
Enable TX bit reversal
On/Off
When you turn this option On, the word
aligner reverses TX parallel data before
transmitting it to the PMA for serialization.
You can only change this static setting using
the Transceiver Reconfiguration Controller.
Enable RX bit reversal
On/Off
When you turn this option On, the
rx_st_
bitrev_ena
port controls bit reversal of the
RX parallel data after it passes from the PMA
to the PCS.
Enable RX byte reversal
On/Off
When you turn this option On, the word
aligner reverses the byte order before
transmitting data. This function allows you to
reverse the order of bytes that were
erroneously swapped. The PCS can swap the
ordering of both 8 and10 bit words.
Enable TX polarity inversion
On/Off
When you turn this option On, the
tx_std_
polinv
port controls polarity inversion of TX
parallel data before transmitting the parallel
data to the PMA.
Enable RX polarity inversion
On/Off
When you turn this option On, asserting
rx_
std_polinv
controls polarity inversion of RX
parallel data after PMA transmission.
UG-01080
2015.01.19
Standard PCS Parameters for the Native PHY
12-23
Stratix V Transceiver Native PHY IP Core
Altera Corporation