Altera Transceiver PHY IP Core User Manual
Page 675
Date
Document
Version
Changes Made
1G/10Gbps Ethernet
PHY IP Core
2.4
Backplane Ethernet
10GBASE-KR PHY
IP Core
2.4
Added descriptions of FEC-related bits: C2[8], CB[26:25].
PHY IP Core for PCI
Express (PIPE)
2.4
Date
Document
Version
Changes Made
1G/10Gbps Ethernet
PHY IP Core
2.3
Changed speed of
rx_recovered_clk
from 125 MHz or 156.25
MHz to 125 MHz or 257.8125 MHz .
Backplane Ethernet
10GBASE-KR PHY
IP Core
2.3
Changed speed of
rx_recovered_clk
from 125 MHz or 156.25
MHz to 125 MHz or 257.8125 MHz .
PHY IP Core for PCI
Express (PIPE)
2.3
Added definition for
pipe_tx_data_valid
Date
Document
Version
Changes Made
PHY IP Core for PCI
Express
2.2
Corrected SDC timing constraint for 62.5 MHz. Clock name is clk_
g1.
Stratix V Native PHY 2.2
Correction: You can specify PLL merging using the
XCVR_TX_PLL_
RECONFIG_GROUP
QSF setting, not the
FORCE_MERGE_PLL
QSF
setting.
Arria V Native PHY 2.2
Correction: You can specify PLL merging using the
XCVR_TX_PLL_
RECONFIG_GROUP
QSF setting, not the
FORCE_MERGE_PLL
QSF
setting.
Arria V GZ Native
PHY
2.2
Correction: You can specify PLL merging using the
XCVR_TX_PLL_
RECONFIG_GROUP
QSF setting, not the
FORCE_MERGE_PLL
QSF
setting.
Cyclone V Native
PHY
2.2
Correction: You can specify PLL merging using the
XCVR_TX_PLL_
RECONFIG_GROUP
QSF setting, not the
FORCE_MERGE_PLL
QSF
setting.
Transceiver Reconfi‐
guration Controller
May 2013
2.2
Update to Transceiver Reconfiguration Controller chapter. Table
16-3 showing resource utilization for Stratix V devices, the timing
unit should be us, microseconds, not ms, milliseconds.
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core
21-15
Additional Information for the Transceiver PHY IP Core
Altera Corporation