Running a simulation testbench, Running a simulation testbench -6 – Altera Transceiver PHY IP Core User Manual
Page 17
The Transceiver PHY Reset Controller IP Core handles all reset sequencing of the transceiver to enable
successful operation. Because the Transceiver PHY Reset Controller IP is available in clear text, you can
also modify it to meet your requirements. For more information about the Transceiver PHY Reset
Controller, refer to Transceiver Reconfiguration Controller IP Core.
To accommodate different reset requirements for different transceivers in your design, instantiate
multiple instances of a PHY IP core. For example, if your design includes 20 channels of the Custom PHY
IP core with 12 channels running a custom protocol using the automatic reset controller and 8 channels
requiring manual control of RX reset, instantiate 2 instances of the Custom PHY IP core and customize
one to use automatic mode and the other to use your own reset logic. For more information, refer to
“Enable embedded reset control” in Custom PHY General Options.
For more information about reset control in Stratix V devices, refer to Transceiver Reset Control in Stratix
V Devices in volume 3 of the Stratix V Device Handbook. For Stratix IV devices, refer to Reset Control and
Power Down in volume 4 of the Stratix IV Device Handbook. For Arria V devices, refer to Transceiver
Reset Control and Power-Down in Arria V Devices. For Cyclone V devices refer to Transceiver Reset
Control and Power Down in Cyclone V Devices.
Related Information
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on page 9-3
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Transceiver PHY Reset Controller IP Core
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Running a Simulation Testbench
When you generate your transceiver PHY IP core, the Quartus
®
II software generates the HDL files that
define your parameterized IP core. In addition, the Quartus II software generates an example Tcl script to
compile and simulate your design in ModelSim.
1-6
Running a Simulation Testbench
UG-01080
2015.01.19
Altera Corporation
Introduction to the Protocol-Specific and Native Transceiver PHYs