Altera Transceiver PHY IP Core - Manual (Page 257)

Name Value Description
Avalon data interfaces On/Off When you turn this option On, the order of
symbols is changed. This option is typically
required if you are planning to import your Low
Latency Transceiver PHY IP Core into a Qsys
system.
Related Information
• User-Coded Reset Controller
• Stratix V Transceiver Clocking
• Transceiver Reset Control in Stratix V Devices
PLL Reconfiguration Parameters
The following table describes the options available on the PLL Reconfiguration tab.
Note: The PLL reconfiguration options are not available for the GT datapath.
Table 10-6: PLL Reconfigurations
Name Value Description
Allow PLL/CDR Reconfiguration On/Off You must enable this option if you plan to
reconfigure the PLLs in your design. This
option is also required to simulate PLL
reconfiguration.
10-10 PLL Reconfiguration Parameters
UG-01080
2015.01.19
Altera Corporation Low Latency PHY IP Core
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