Altera Transceiver PHY IP Core - Manual (Page 649)

Stratix IV devices that include transceivers must use the ALTGX_RECONFIG IP Core to implement
dynamic reconfiguration. The ALTGX_RECONFIG IP Core always includes the following two serial
buses:
•
reconfig_from[<n>16:0]
— this bus connects to all the channels in a single quad. <n> is the number
of quads connected to the ALTGX_RECONFIG IP Core.
•
reconfig_togxb[3:0]
—this single bus connects to all transceiver channels.
If you select additional functionality in the MegaWizard Plug-In Manager for the ALTGX_RECONFIG IP
Core, the IP core adds signals to support that functionality. For more information about the
ALTGX_RECONFIG IP Core, refer to ALTGX_RECONFIG Megafunction User Guide for Stratix IV
Devices in volume 3 of the Stratix IV Device Handbook.
Related Information
ALTGX_RECONFIG Megafunction User Guide for Stratix IV Devices
Differences Between XAUI PHY Parameters for Stratix IV and Stratix V
Devices
Table 20-2: Comparison of ALTGX Megafunction and XAUI PHY Parameters
ALTGX Parameter Name (Default Value) XAUI PHY Parameter Name Comments
Number of channels Number of XAUI
interfaces
In Stratix V devices, this parameter is
locked to 1 (for 4 channels). You
cannot change it in the current
release.
Train receiver clock and data
recover (CDR) from pll_inclk (On) Not available as
parameters in the
MegaWizard Plug-In
Manager interface
Use assignment editor to make these
assignment TX PLL bandwidth mode (Auto)
RX CDR bandwidth mode (Auto)
UG-01080
2013.12.20
Differences Between XAUI PHY Parameters for Stratix IV and Stratix V Devices 20-3
Migrating from Stratix IV to Stratix V Devices Overview Altera Corporation
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