Altera Transceiver PHY IP Core - Manual (Page 691)

Date Document
Version
Changes Made
Low Latency PHY
February 2012 1.5
• Added register definitions for Low Latency PHY.
Deterministic Latency PHY
February 2012 1.5
• Removed
pma_rx_signaldetect
register. The Deterministic
Latency PHY does not support this functionality.
• Updated the definition of deterministic latency word alignment
mode to include the fact that the word alignment pattern, which
is currently forced to K28.5 = 0011111010 is always placed in the
least significant byte (LSB) of a word with a fixed latency of 3
cycles.
Transceiver Reconfiguration Controller
February 2012 1.5
• Added DFE.
Introduction
December 2011 1.4
• Revised discussion of embedded reset controller to include the
fact that this reset controller can be disabled for some transceiver
PHYs.
10GBASE-R
December 2011 1.4
• Removed description of calibration block powerdown register
(0x021) which is not available for this transceiver PHY.
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
XAUI
December 2011 1.4
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
• Added Arria II GX to device support table.
Interlaken
December 2011 1.4
• Changed access mode for RX equalization, pre-CDR reverse
serial loopback, and post-CDR reverse serial loopback to write
only (WO).
• Removed optional
rx_sync_word_err
,
rx_scrm_err
, and
rx_
framing_err
status bits.
• Changed definition of
phy_mgmt_clk_reset
. This signal is
active high and level sensitive.
PHY IP Core for PCI Express (PIPE)
UG-01080
2015.01.19
Revision History for Previous Releases of the Transceiver PHY IP Core 21-31
Additional Information for the Transceiver PHY IP Core Altera Corporation
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