Altera Transceiver PHY IP Core - Manual (Page 489)

Parameter Range Description
Use external TX PLL On/Off When you turn this option On, the Native PHY
does not include TX PLLs. Instead, the Native
PHY includes a input clock port for connection to
the fast clock from an external PLL,
ext_pll_
clk[<p>-1:0]
that you can connect to external
PLLs. Use feature when need to perform TX PLL
switching between fractional PLL and a CMU
PLL.
Number of TX PLLs 1–4 Specifies the number of TX PLLs that can be used
to dynamically reconfigure channels to run at
multiple data rates. If your design does not
require transceiver TX PLL dynamic reconfigura‐
tion, set this value to 1. The number of actual
physical PLLs that are implemented depends on
the selected clock network. Each channel can
dynamically select between n PLLs, where n is the
number of PLLs specified for this parameter.
Note: Refer to Transceiver Clocking in
Cyclone V Devices chapter for more
details.
Main TX PLL logical index 0–3 Specifies the index of the TX PLL used in the
initial configuration.
Number of TX PLL reference
clocks
1–5 Specifies the total number of reference clocks that
are used by all of the PLLs.
Related Information
Cyclone V Device Handbook Volume 2: Transceivers
TX PLL Parameters
This section allows you to define multiple TX PLLs for your Native PHY. The Native PHY GUI provides a
separate tab for each TX PLL.
Table 15-5: TX PLL Parameters
Parameter Range Description
PLL type CMU This is the only PLL type available.
15-6 TX PLL Parameters
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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