Altera Transceiver PHY IP Core - Manual (Page 546)

Figure 16-5: Reconfiguration Tab of Native Transceiver PHYs
Note: If you dynamically reconfigure PLLs, you must provide your own reset logic by including the
Altera Reset Controller IP Core or your own custom reset logic in your design. For more informa‐
tion about the Altera-provided reset controller, refer to Chapter 17, Transceiver PHY Reset
Controller IP Core.
For more information about the Stratix V reset sequence, refer to Transceiver Reset Control in Stratix V
Devices in volume 2 of the Stratix V Device Handbook. For Arria V devices, refer to Transceiver Reset
Control and Power-Down in Arria V Devices. For Cyclone V devices refer to Transceiver Reset Control and
Power Down in Cyclone V Devices.
When you specify multiple PLLs, you must use the QSF assignment,
XCVR_TX_PLL_RECONFIG_GROUP
, to
identify the PLLs within a reconfiguration group using the Assignment Editor. The
XCVR_TX_PLL_RECONFIG_GROUP
assignment identifies PLLs that the Quartus II Fitter can merge. You can
assign TX PLLs from different transceiver PHY IP core instances to the same group.
Note: You must create the
XCVR_TX_PLL_RECONFIG_GROUP
even if one transceiver PHY IP core instance
instantiates multiple TX PLLs.
UG-01080
2015.01.19
Transceiver Reconfiguration Controller PLL Reconfiguration 16-29
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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